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CC1312R: FLASH write / NVSCC26XX driver related questions

Part Number: CC1312R

Hi,

According to TRM documentation:
"The FLASH memory is organized as a set of 8-KB blocks that can be individually erased. An individual 64-bit word can be programmed to change bits from 1 to 0. .... A row is comprised of 2048 bits (or 256 bytes). The FLASH memory is divided evenly into physical rows."

1. Does this mean that minimum phisicaly written data to the flash should be at least 64-bits (8bytes)? I see that NVS driver pass data with size smaller than 8 bytes to the FlashProgram() function, but what happened inside is not clear for me.

2. Should be data aligned to the start of the flash row (like offset value to not be 3 for instance)?

3. Should data be aligned to the end of the flash row (to not be written a word on two pages, like one half on one page and the other half on other) or the FlashProgram() function handle this?

Regards,

Dimitar Devedzhiev

  • Hi Dimitar

    Please allow me some time to look into this. The R&D team responsible for the driver is located in Dallas, so I will try to reach out to them for help.

    BR

    Siri

  • Hi Dimitar

    What the TRM tries to state is that up to 64 bits can be written in one operation (in HW).

    The ROM code, and the Flash IP HW can write minimum 1 byte, and the user specifies how many bytes he wants to program, and the flash API makes sure that this is done with the required number of write operations in HW.

    Note that there are limitations on how many times you can write to a flash row before the flash sector containing the row, must be erased. The maximum number of write operations per row before sector erase is given in the data sheet.

    No alignment is required from the application side.

    BR

    Siri

  • Hi Siri,

    Let's say that I am going to write 16bits (two bytes) variable at the offset 7 from the NVS region (8-th byte from row and last from first 64bits). Should I count their write as two writes to the row?

    Regards

    Dimitar Devedzhiev

  • Hi Dimitar

    Again I had to consult R&D, and here is their response:

    When customer is using NVS API, customer only provides Flash starting address and number of bytes to programming. Inside of ROM Flash API, ROM Flash API will figure out how many Flash writes are required.

    For example, for 2 byte writing to Flash, there are two possibility.

    1. If staring address + len (number of bytes) is single row,  only one flash write is required.
    2. If starting address + len (number of bytes) is crossing the row boundary (your example), the ROM Flash API will use two writes. One write is for 1 byte. The second write will be in next row for 1 bytes. 

    For another examples, if customer wants to write 20 bytes to flash, here is number of flash write possibility (internal Flash API). It depends on flash staring address.

    1. 8 bytes + 8 bytes + 4 bytes è 3 Flash writes (internal)
    2. 4 bytes + 8 bytes + 8 bytes è 3 flash writes (internal)
    3. 2 bytes + 8 bytes + 8 bytes + 2 bytes è 4 flash writes (internal)

    Anyway, if customer is using NVS flash API, one NVS flash write API is called, the internal ROM Flash API will break down into multiple Flash write operations.

    hope this answered your questions.

    BR

    Siri

  • Hi Siri,

    Thank you, this answers to my question, but I have another one (might be more simple):

    Can the NVSCC26XX driver be used before starting RTOS (before BIOS_start())?

    Regards,

    Dimitar Devedzhiev  

  • Hi Dimitar

    I am leaving for vacation now, so could you please post this last question in a new thread, and it will be assigned to someone else in my team that will follow up.

    BR

    Siri