CC1310: IO pin edge interrupt latency

I have a question regarding IO pin interrupt latency.

A 100KHz signal is feed into the "IN_PIN", and inside the gpio_isr another Output pin is toggled upon entry.

I get about 2.7uS latency from the input signal rising edge, to the Output is toggled.

I did not expect the latency to be so high, 2.7uS is about 130 cycles at 48MHz.

Where does this latency come from ?

Note, the code is running without TIOS. See code-snap below.

IOCPinTypeGpioInput(IN_PIN);

// Register the interrupt handler.
IntRegister(INT_AON_GPIO_EDGE, gpio_irq);
IntPrioritySet(INT_AON_GPIO_EDGE, INT_PRI_LEVEL0);
IOCIOIntSet(IN_PIN, IOC_INT_ENABLE, IOC_RISING_EDGE);