CC1310: Add the interval

Hi Cherry, 

This could be achieved by controlling the CS pin manually using a GPIO and sending one byte at a time using separate SPI_transfer. With this approach you don't need to modify the SPI driver code in the SDK.

I unassigned the CSn pin in the SPI driver inside CC1310_LAUNCHXL.c:

const SPICC26XXDMA_HWAttrsV1 spiCC26XXDMAHWAttrs[CC1310_LAUNCHXL_SPICOUNT] = {
    {
        .baseAddr           = SSI0_BASE,
        .intNum             = INT_SSI0_COMB,
        .intPriority        = ~0,
        .swiPriority        = 0,
        .powerMngrId        = PowerCC26XX_PERIPH_SSI0,
        .defaultTxBufValue  = 0xFF,
        .rxChannelBitMask   = 1<<UDMA_CHAN_SSI0_RX,
        .txChannelBitMask   = 1<<UDMA_CHAN_SSI0_TX,
        .mosiPin            = CC1310_LAUNCHXL_SPI0_MOSI,
        .misoPin            = CC1310_LAUNCHXL_SPI0_MISO,
        .clkPin             = CC1310_LAUNCHXL_SPI0_CLK,
        .csnPin             = PIN_UNASSIGNED, // <- csn pin controlled by software
        .minDmaTransferSize = 10
    },

I tried out the following code in the spimaster example:

    /* Initialize master SPI transaction structure */
    txChar = masterTxBuffer[0];
    transaction.count = 1;
    transaction.txBuf = (void *) &txChar;
    transaction.rxBuf = (void *) masterRxBuffer;

    // deassert CS pin
    GPIO_write(Board_SPI_MASTER_CSn, 0);
    
    for (i = 0; i < SPI_MSG_LENGTH; i++){
        txChar = masterTxBuffer[i];
        transferOK = SPI_transfer(masterSpi, &transaction);
        if (!transferOK) {
            while(1){};
        }
    }
    
    // assert CS pin
    GPIO_write(Board_SPI_MASTER_CSn, 1);

and obtained the following transaction on the logic analyzer:

The interval between each byte transaction ends up being between 11 and 12us. It's hard to achieve tighter intervals between the bytes without modifying the SPI driver code. Would this work for the costumer?

Regards,

Fausto

Hi Cherry,

The SPI driver code for CC1310 is located in <SDK>/source/ti/drivers/SPI.h and SPI.c. The device specific code is located in <SDK>/source/ti/drivers/spi/SPICC26XX.h and SPICC26XX.c . If the client wants to go even more low-level they will have to modify the ssi module in driverlib, located at <SDK>/source/ti/devices/cc13x0/driverlib/ssi.h and ssi.c

Regards,

Fausto

Hi Cherry,

When setting up the transfer in DMA mode the driver will not interfere with the SPI module once the transaction is started. the DMA HW module will automatically load bytes in the SPI TX FIFO and the SPI IP will transfer data as fast as it is allowed to run. Unfortunately there is no parameter or HW configuration of the SPI module allowing you to select the time interval between consecutive bytes (I couldn't find any setting in the TRM for the SSI module regarding this). The recorded time interval from your last post derive from the execution time of the code between one byte and the next. Therefore I don't think this use case is supported by our device. The customer will have to use either ~2 clock cycles (DMA transaction), ~11 clock cycles (non-DMA transaction) or implement a scaled down version of the SPI driver where they can have more accurate timing control.

Regards,

Fausto