CC1350: Noise in DCDC inductor

DCDC performance is highly dependent on the inductor used. I would use the TDK part used in the ref designs. I believe it's a lot of app notes from different vendors on general DCDC usage that could cover this in more detail than SWRA640.

Hi Olav,

Could you test using the internal LDO to verify if a good and bad device draw the same current using the LDO? To test this you need to remove the inductor and modify the CCFG file to use the LDO.

In the voltage plots you mentioned that this are for VDDR, however looking at the voltage level this seem to be for VDDS. VDDR voltage should be around 1.7 V.

Hi Diego,

You are of course correct and I measured VDDS instead, apologies.. Here are the actual measurements of VDDR in DCDC mode:

Smaller timescale:

I soldered off the inductors and disabled the DCDC, and they also draw different currents in LDO mode (3.48uA on the bad device, versus 2.72 on the good one). I'll attach the current draw plots as before (good in green, bad in red), let me know if there is anything else I should capture.

Together:

Individual:

Thank you

Hi Olav,

Would it be possible to get plots of VDDR with a higher sample rate?

in your test code are you using any peripherals or setting certain pins as input or outputs? Or are the devices just going into standby?

This is the maximum sample rate of my oscilloscope (50 MS/s) at a smaller timescale. I'm assuming the points where it "jumps" are the interesting parts.

The good device looks pretty much like this every time:

While the bad device is a mix between these smaller and larger jumps:

I will attach an export of 250ms data from both channels if you want to poke around: analog.csv

I'm instrumenting a production test image, so the I2C and GPIO peripherals are enabled prior to going to standby (I2C clock is disabled after use though). At standby I have two pins in output and one input. I didn't think to disable it since I can move the cc1350 chip between different PCBAs and see the same behavior, but I will make a test program that just goes to standby and see if it makes a difference.

Seeing that you also have higher current consumption with the internal LDO, it makes me believe that there may be peripheral or gpio that causes the higher current consumption. Check that pins that have pull ups or pull downs are set to a state that don't draw current and output pins are not sourcing current to another component. Please let us know the results with the program that just goes into standby.

That makes sense, but I am not able to remove the noise nor the higher current consumption. I tried a couple things to try and pin down the cause:

1. Made a test program that simply enters standby. No peripherals enabled, GPIOs untouched. Both devices are still in LDO mode. Good device in green, bad in red:

Quite a bit higher average current drain, probably caused by some active components that need to be put in reset.

2. Soldered off all other active external components, including pull-resistors on GPIOs, to exclude interference from them. This reduces the standby currents again, but the bad device is still visibly different from the good one, and draws more current. Very similar current drains to the production test program I used above:

3. Modified the test program to enable the GPIO peripheral and drive all pins low (just to make sure they are not floating). Very little difference

What  is new/ different in this design vs what you done before with CC1350? 

Hi Olav,

Could you desolder the bad device and measure resistance of each pin to ground and post the results?

The design is quite similar to another design we have, where we have not observed this error mode. Relevant differences:

1. DCDC inductor is rotated 90 degress (same inductor)
2. DCDC bulk cap on VDDR (C6 in the OP image) is significantly larger (22uF in this design, 2.2uF in previous)
   • This cap is also placed outside the power path in this design, as mentioned in the OP

Since we're observing the noisy condition also in LDO mode, I tried to reduce the bulk capacitance near the DCDC inductor (C6 again). Reducing this to 2.2uF seems to remove the noisy behavior. This also removed the noise with the DCDC enabled again. I therefore tried to play with the ccfg option SET_CCFG_MODE_CONF_VDDR_CAP, but had no luck replicating the workaround with the 22uF cap. Since 22uF is used in the reference design, I'm not comfortable with reducing it without knowing the root cause of the noise.

Hi Diego,

I can do that, I assume you meant the chip (and not on the PCBA). This is the RSM variant, and I used pin 3 as the ground connection. NC just means my multimeter was unable to measure a connection at all

I had to get some new probes and use a different multimeter, but here I have repeated the measurements on all the pins:

I tried both pin 7 and pin 29 as VSS this time around, and got similar results, hope this is better.

Edit: I seem to have pressed the resolve-button by accident, sorry, I can't seem to undo that..

Resistance on some of the pins seems low. Could you please do the same measurements on a good device that you have?

Absolutely, repeated measurements with two good devices, and another bad one.

Small update, we have implemented another test step to compare standby current directly after assembly and after the rest of our production tests. Since it seems your suspicion is damaged hardware, we want to rule out the tests themselves from damaging the chips. I have little reason to believe the tests would be damaging, but I'll post an update if I see anything interesting.

Regarding the comparison between good&bad devices above: I notice DCDC_SW is significantly lower on the bad devices, is this the pin you were thinking of? If so, what could cause this, and what effects does it have?

Thanks

Hi Olav,

Yes my suspicion was that a pin may be damaged and causing increased current consumption. We have seen ESD causing damage to pins and increasing current consumption.

Have you been able to compare current consumption directly after assembly and after the rest of your production tests? Is your production space/equpment ESD safe?

I see. We are using an external professional factory for production, so we are quite confident the production and test environments are ESD safe. I will follow up with the factory.

I don't have any numbers yet, it may be a while before we are running a new batch, as we currently have a lot of inventory. As mentioned we only see this in about 2% of devices, so I need some scale to get new failing samples. But I will come with an update when we have some numbers from the new test to compare.

Thanks. Please do let us know once you have new numbers.

Hi Olav,

are you using the RGZ package device?

To rule out a layout issue or inductor issue, If you are using the RGZ package and if you have a CC1350 Launchpad on hand would you be able to solder one of the bad devices to the launchpad and measure the standby current of the device mounted on the launchpad?

Hi Diego,

Very good idea, but unfortunately this is the RSM package..