Other Parts Discussed in Thread: TEST2
Hi Team,
Reading register data, RSSI and LQI are always at values that change only at certain times when it is not receiving a signal. So it's hard to get the RSSI and LQI values causing it's impossible to know what the antenna looks like. The customer has attempted to read directly to corresponding register 0x33 [0xF3] 0x34[0xF4], Also takes an open register setting, 0x07: PKTCTRL1 reads 0x05 and two bits after BUFFER.
- Is it required to read RSSI and LQI values at a specific point in time, for example, after receiving a packet?
- Is it required to configure any specific registers or settings to read RSSI and LQI correctly?
- Can the following hardware and antenna configurations affect RSSI and LQI read?
- Are there any specific signal conditions or environmental factors that could affect RSSI and LQI reads?
The setting is as follows:
typedef struct
{
uint8_t iocfg0; // GDO0 Output Pin Configuration
uint8_t fifothr; // RX FIFO and TX FIFO Thresholds
uint8_t sync1; // Sync Word, High Byte
uint8_t sync0; // Sync Word, Low Byte
uint8_t pktlen; // Packet Length
uint8_t pktctrl0; // Packet Automation Control
uint8_t fsctrl1; // Frequency Synthesizer Control
uint8_t freq2; // Frequency Control Word, High Byte
uint8_t freq1; // Frequency Control Word, Middle Byte
uint8_t freq0; // Frequency Control Word, Low Byte
uint8_t mdmcfg4; // Modem Configuration
uint8_t mdmcfg3; // Modem Configuration
uint8_t mdmcfg2; // Modem Configuration
uint8_t mdmcfg1; // Modem Configuration
uint8_t deviatn; // Modem Deviation Setting
uint8_t mcsm0; // Main Radio Control State Machine Configuration
uint8_t foccfg; // Frequency Offset Compensation Configuration
uint8_t agcctrl2; // AGC Control
uint8_t agcctrl1; // AGC Control
uint8_t worctrl; // Wake On Radio Control
uint8_t fscal3; // Frequency Synthesizer Calibration
uint8_t fscal2; // Frequency Synthesizer Calibration
uint8_t fscal1; // Frequency Synthesizer Calibration
uint8_t fscal0; // Frequency Synthesizer Calibration
uint8_t test2; // Various Test Settings
uint8_t test1; // Various Test Settings
uint8_t test0; // Various Test Settings
} RF_SETTINGS;
static RF_SETTINGS E07x_InitSetting = {
0x06, // IOCFG0 GDO0 Output Pin Configuration
0x47, // FIFOTHR RX FIFO and TX FIFO Thresholds
0x7A, // SYNC1 Sync Word, High Byte
0x0E, // SYNC0 Sync Word, Low Byte
0x14, // PKTLEN Packet Length
0x05, // PKTCTRL0 Packet Automation Control
0x06, // FSCTRL1 Frequency Synthesizer Control
0x10, // FREQ2 Frequency Control Word, High Byte
0xB1, // FREQ1 Frequency Control Word, Middle Byte
0x3B, // FREQ0 Frequency Control Word, Low Byte
0xF5, // MDMCFG4 Modem Configuration
0x83, // MDMCFG3 Modem Configuration
0x13, // MDMCFG2 Modem Configuration
0x02, // MDMCFG1 Modem Configuration
0x31, // DEVIATN Modem Deviation Setting
0x18, // MCSM0 Main Radio Control State Machine Configuration
0x16, // FOCCFG Frequency Offset Compensation Configuration
0x43, // AGCCTRL2 AGC Control
0x49, // AGCCTRL1 AGC Control
0xFB, // WORCTRL Wake On Radio Control
0xE9, // FSCAL3 Frequency Synthesizer Calibration
0x2A, // FSCAL2 Frequency Synthesizer Calibration
0x00, // FSCAL1 Frequency Synthesizer Calibration
0x1F, // FSCAL0 Frequency Synthesizer Calibration
0x81, // TEST2 Various Test Settings
0x35, // TEST1 Various Test Settings
0x09, // TEST0 Various Test Settings
};
static uint8_t E07x_Config(uint32_t frequency, uint32_t data_rate, uint32_t frequency_dev, uint32_t bandwidth,
int8_t output_power, uint16_t preamble_size, uint16_t sync_word, uint8_t crc)
{
uint8_t result;
uint8_t reg_value;
/* Calculating: Carrier frequency
* Register start address 0x0D */
result = E07x_SetFrequency(frequency);
if (result != 0)
return 1;
/* Calculation: Air speed
* MDMCFG4 MDMCFG3 Register address :0x10 0x11 */
E07x_SetDataRate(data_rate);
/* Calculation: Frequency Bias
* DEVIATN Register address:0x15 */
E07x_SetFrequencyDeviation(frequency_dev);
/* Calculate: Receive bandwidth
* MDMCFG4 Register address:0x10 */
E07x_SetChannelBandwidth(bandwidth);
/* Calculation: Output power
* Register address:0x3E */
E07x_SetOutputPower(output_power);
/* Modulation mode
* MDMCFG2 Register address:0x12 */
E07x_SetModulation(1); // GFSK
/* Preamble length
* MDMCFG1 Register address:0x13 */
if (preamble_size > 7)
return 1; // Parametric check
E07x_InitSetting.mdmcfg1 &= 0x8F; // Clear
E07x_InitSetting.mdmcfg1 |= (preamble_size << 4); // set
/* Synchronized words
* SYNC1 SYNC0 Register address:0x04 0x05 */
E07x_InitSetting.sync1 = (uint8_t)((sync_word >> 8) & 0xFF); // high Byte
E07x_InitSetting.sync0 = (uint8_t)(sync_word & 0xFF); // low Byte
/* CRC switch
* PKTCTRL0 Register address:0x08 bit2 */
if (crc > 1)
return 1; // Parametric check which can only be 0 or 1
if (crc)
{
E07x_InitSetting.pktctrl0 |= 0x04; // turn on
}
else
{
E07x_InitSetting.pktctrl0 &= 0xFB;
}
/* The packet length, which defaults to variable length mode and is placed in the first byte of data
* PKTCTRL0 Register address:0x08 bit[1:0] */
E07x_InitSetting.pktctrl0 &= 0xFC; // clear
E07x_InitSetting.pktctrl0 |= 0x01; // 0x01 mode (Variable length)
/* Note: If you want to use the official SmartRF Studio configuration parameters entirely, you can comment directly on the modified function above */
/* Write the calculated E07x_InitSetting parameter table to the module */
E07x_SetRegister(0x02, E07x_InitSetting.iocfg0);
E07x_SetRegister(0x03, E07x_InitSetting.fifothr);
E07x_SetRegister(0x04, E07x_InitSetting.sync1);
E07x_SetRegister(0x05, E07x_InitSetting.sync0);
E07x_SetRegister(0x07, 0x05);
E07x_SetRegister(0x08, E07x_InitSetting.pktctrl0);
E07x_SetRegister(0x0B, E07x_InitSetting.fsctrl1);
E07x_SetRegister(0x0D, E07x_InitSetting.freq2);
E07x_SetRegister(0x0E, E07x_InitSetting.freq1);
E07x_SetRegister(0x0F, E07x_InitSetting.freq0);
E07x_SetRegister(0x10, E07x_InitSetting.mdmcfg4);
E07x_SetRegister(0x11, E07x_InitSetting.mdmcfg3);
E07x_SetRegister(0x12, E07x_InitSetting.mdmcfg2);
E07x_SetRegister(0x13, E07x_InitSetting.mdmcfg1);
E07x_SetRegister(0x15, E07x_InitSetting.deviatn);
E07x_SetRegister(0x18, E07x_InitSetting.mcsm0);
E07x_SetRegister(0x19, E07x_InitSetting.foccfg);
E07x_SetRegister(0x1B, E07x_InitSetting.agcctrl2);
E07x_SetRegister(0x1C, E07x_InitSetting.agcctrl1);
E07x_SetRegister(0x20, E07x_InitSetting.worctrl);
E07x_SetRegister(0x23, E07x_InitSetting.fscal3);
E07x_SetRegister(0x24, E07x_InitSetting.fscal2);
E07x_SetRegister(0x25, E07x_InitSetting.fscal1);
E07x_SetRegister(0x26, E07x_InitSetting.fscal0);
E07x_SetRegister(0x2C, E07x_InitSetting.test2);
E07x_SetRegister(0x2D, E07x_InitSetting.test1);
// E07x_SetRegister( 0x2E, E07x_InitSetting.test0); //Discover: Setting TEST0 causes custom calculated frequency to shift
//Symptom(s): When the frequency point is set to less than 411MHz, the frequency point is locked at 411MHz. Frequency point switching is normal when the frequency point is set to greater than 411MHz
// Recommendation: Unannotate TEST0 when the official SmartRF Studio parameters are fully enabled. Leave a comment when calculating with free parameters
/* Complementary: Channel coding (which can be used for frequency hopping) register addresses : 0x0A */
E07x_SetRegister(0x0A, 0);
/* Supplementary: Turns off the address filtering. register address : 0x07 */
reg_value = E07x_GetRegister(0x07);
reg_value &= 0xFC; // clear
E07x_SetRegister(0x07, reg_value);
/* Supplementary: Configure the output power. register address : 0x3E */
E07x_SetRegisters(0x3E, E07x_PaTabel, 8);
return 0;
}
#define E07_FREQUENCY_START 433000000 // 433 MHz
#define E07_DATA_RATE 1200
#define E07_FREQUENCY_DEVIATION 14300
#define E07_BANDWIDTH 58000
#define E07_OUTPUT_POWER 10
#define E07_PREAMBLE_SIZE 4
#define E07_SYNC_WORD 0x2DD4
#define E07_IS_CRC 1
result = E07x_Config(E07_FREQUENCY_START,
E07_DATA_RATE,
E07_FREQUENCY_DEVIATION,
E07_BANDWIDTH,
E07_OUTPUT_POWER,
E07_PREAMBLE_SIZE,
E07_SYNC_WORD,
E07_IS_CRC);
Could you please help check this case? Thanks.
Best Regards,
Cherry
