I’m communicating between cc1200’s at a symbol rate of 21K and RBW 26Khz using two different packet formats.
Format A transmits one byte of preamble for settling only, sync word = 2 bytes. The receiver does not gate preamble and only looks for sync. With RBW >= Bit Rate. PER is error free and approximately the same at RF input levels from 0dbm down to -105dbm but RSSI levels do not read correctly at RF inputs above -55dbm. They are limited at around -55dbm.
Format B transmits 30 bytes of preamble. The receiver gates preamble via the cc1200 GPIO/MCU (not cc1200 internal), sync word = 4 bytes. Preamble detection is reliable from -55dbm down to threshold but becomes intermittent at RF input levels above approximately -50dbm. Proper preamble detection is critical for active channel detection and preamble gating in this system for from 0dbm to threshold. At all signal levels, preamble detection time with pre-loaded FS calibration and after SRX takes ~1.155ms this is 99us longer than calculated on the excel spread sheet from SWRA428A.
While implementing RX_CONFIG_LIMITATION = 1, I started with the information from the user guide and Siri (see below from Siri), then tested and modified a bit for better results but I have not been able to find the a combination of settings that allow proper RSSI reporting and preamble detection from ~0dbm to RX threshold.
“You can use RX_CONFIG_LIMITATION = 1, but remember that the AGC_CFG1.AGC_WIN_SIZE should be incremented by 1 and the wait time between AGC gain adjustment programmed through AGC_CFG1.AGC_SETTLE_WAIT should be doubled (compared to what SmartRF Studio recommends when RX_CONFIG_LIMITATION = 0)
AGC_SETTLE_WAIT will affect T1, which again affects the PQT response time
PQT Response Time = T0 + T1
The PQT response time is the time it takes from entering RX mode until PQT_VALID is asserted (the time it takes in RX for the radio to figure out if there is a preamble on the air or not).”
These are the my questions:
1. Regarding format A (2 byte sync, no preamble gating), are there register settings that will allow full range RSSI reporting without compromising RX sensitivity/BER?
2. Regarding format B (4 byte sync, with preamble gating), are there register settings that will allow full range preamble/bit detection without compromising RX sensitivity/BER or RSSI reporting?
3. What could be the reason for the slower than calculated preamble detection?
Below are the base register settings:
{CC1200_IOCFG3, 0x06},
{CC1200_IOCFG2, 0x0B},
{CC1200_IOCFG1, 0x30},
{CC1200_IOCFG0, 0x06},
{CC1200_SYNC3, 0x93},
{CC1200_SYNC2, 0x0B},
{CC1200_SYNC1, 0x51},
{CC1200_SYNC0, 0xDE},
{CC1200_SYNC_CFG1, 0x4A},
{CC1200_SYNC_CFG0, 0x13},
{CC1200_DEVIATION_M, 0xD7},
{CC1200_MODCFG_DEV_E, 0x01},
{CC1200_DCFILT_CFG, 0x5D},
{CC1200_PREAMBLE_CFG1, 0x10},
{CC1200_PREAMBLE_CFG0, 0x8A},
{CC1200_IQIC, 0xCB},
{CC1200_CHAN_BW, 0x90},
{CC1200_MDMCFG1, 0x40},
{CC1200_MDMCFG0, 0x05},
{CC1200_SYMBOL_RATE2, 0x81},
{CC1200_SYMBOL_RATE1, 0x34},
{CC1200_SYMBOL_RATE0, 0x05},
{CC1200_AGC_REF, 0x33},
{CC1200_AGC_CS_THR, 0xEC},
{CC1200_AGC_GAIN_ADJUST, 0x00},
{CC1200_AGC_CFG3, 0xB1},
{CC1200_AGC_CFG2, 0x20},
{CC1200_AGC_CFG1, 0x65},
{CC1200_AGC_CFG0, 0x8F},
{CC1200_FIFO_CFG, 0x00},
{CC1200_DEV_ADDR, 0x00},
{CC1200_SETTLING_CFG, 0x03},
{CC1200_FS_CFG, 0x12},
{CC1200_WOR_CFG1, 0x08},
{CC1200_WOR_CFG0, 0x21},
{CC1200_WOR_EVENT0_MSB, 0x00},
{CC1200_WOR_EVENT0_LSB, 0x00},
{CC1200_RXDCM_TIME, 0x00},
{CC1200_PKT_CFG2, 0x00},
{CC1200_PKT_CFG1, 0x41},
{CC1200_PKT_CFG0, 0x00},
{CC1200_RFEND_CFG1, 0x0F},
{CC1200_RFEND_CFG0, 0x00},
{CC1200_PA_CFG1, 0x5F},
{CC1200_PA_CFG0, 0x54},
{CC1200_ASK_CFG, 0x0F},
{CC1200_PKT_LEN, 0x1E},
{CC1200_IF_MIX_CFG, 0x1C},
{CC1200_FREQOFF_CFG, 0x00},
{CC1200_TOC_CFG, 0x0B},
{CC1200_MARC_SPARE, 0x00},
{CC1200_ECG_CFG, 0x00},
{CC1200_MDMCFG2, 0x08},
{CC1200_EXT_CTRL, 0x01},
{CC1200_RCCAL_FINE, 0x00},
{CC1200_RCCAL_COARSE, 0x00},
{CC1200_RCCAL_OFFSET, 0x00},
{CC1200_FREQOFF1, 0x00},
{CC1200_FREQOFF0, 0x00},
{CC1200_FREQ2, 0x5B},
{CC1200_FREQ1, 0x80},
{CC1200_FREQ0, 0x00},
{CC1200_IF_ADC2, 0x02},
{CC1200_IF_ADC1, 0xEE},
{CC1200_IF_ADC0, 0x10},
{CC1200_FS_DIG1, 0x07},
{CC1200_FS_DIG0, 0xAF},
{CC1200_FS_CAL3, 0x00},
{CC1200_FS_CAL2, 0x20},
{CC1200_FS_CAL1, 0x40},
{CC1200_FS_CAL0, 0x0E},
{CC1200_FS_CHP, 0x28},
{CC1200_FS_DIVTWO, 0x03},
{CC1200_FS_DSM1, 0x00},
{CC1200_FS_DSM0, 0x33},
{CC1200_FS_DVC1, 0xFF},
{CC1200_FS_DVC0, 0x17},
{CC1200_FS_LBI, 0x00},
{CC1200_FS_PFD, 0x00},
{CC1200_FS_PRE, 0x6E},
{CC1200_FS_REG_DIV_CML, 0x1C},
{CC1200_FS_SPARE, 0xAC},
{CC1200_FS_VCO4, 0x14},
{CC1200_FS_VCO3, 0x00},
{CC1200_FS_VCO2, 0x00},
{CC1200_FS_VCO1, 0x00},
{CC1200_FS_VCO0, 0xB5},
{CC1200_SERIAL_STATUS, 0x00},
Format A TX:
{CC1200_PREAMBLE_CFG1, 0x08},
{CC1200_PREAMBLE_CFG0, 0x0A},
{CC1200_DEVIATION_M, 0x6F},
{CC1200_SYNC_CFG1, 0x4A},
{CC1200_PKT_LEN, 67},
{CC1200_IOCFG2, 0x65},
{CC1200_IOCFG0, 0x66},
{CC1200_PKT_CFG0, 0x00},
Format A RX:
{CC1200_PREAMBLE_CFG1, 0x08},
{CC1200_PREAMBLE_CFG0, 0x8B},
{CC1200_DEVIATION_M, 0xD7},
{CC1200_SYNC_CFG1, 0x4A},
{CC1200_PKT_LEN, 67},
{CC1200_IOCFG2, 0x0B},
{CC1200_IOCFG0, 0x06},
{CC1200_AGC_CFG3, 0xB1},
{CC1200_AGC_CFG1, 0x5B},
{CC1200_AGC_CFG0, 0x87},
{CC1200_PKT_CFG0, 0x00},
Format B TX:
{CC1200_PREAMBLE_CFG1, 0x34},
{CC1200_PREAMBLE_CFG0, 0x8A},
{CC1200_DEVIATION_M, 0x6F},
{CC1200_SYNC_CFG1, 0xAA},
{CC1200_PKT_LEN, 20},
{CC1200_IOCFG2, 0x65},
{CC1200_IOCFG0, 0x66},
{CC1200_PKT_CFG0, 0x0C},
Format B RX:
{CC1200_PREAMBLE_CFG1, 0x30},
{CC1200_PREAMBLE_CFG0, 0x8B},
{CC1200_DEVIATION_M, 0xD7},
{CC1200_SYNC_CFG1, 0xAA},
{CC1200_PKT_LEN, 20},
{CC1200_IOCFG2, 0x0B},
{CC1200_IOCFG0, 0x06},
{CC1200_AGC_CFG3, 0xB1},
{CC1200_AGC_CFG1, 0x5B},
{CC1200_AGC_CFG0, 0x87},
{CC1200_PKT_CFG0, 0x0C},