Other Parts Discussed in Thread: TEST2
Dear Team,
I am currently utilizing the CC1101 chip, where I have initiated the power-down mode by implementing the following configuration:
void CC1101_PowerDown() { SpiStrobe(CC1101_SIDLE); SpiStrobe(CC1101_SPWD); }
My register configuration
#define VAL_IOCFG2 0x07//0x29 #define VAL_IOCFG1 0x2E #define VAL_IOCFG0 0x06 #define VAL_FIFOTHR 0x47 #define VAL_SYNC1 0xD3 #define VAL_SYNC0 0x91 #define VAL_PKTLEN 0x61//0xFF #define VAL_PKTCTRL1 0x05 #define VAL_ADDR 0x00 #define VAL_CHANNR 0x00 #define VAL_FSCTRL1 0x06 #define VAL_FSCTRL0 0x00 #define VAL_FREQ2 0x10 #define VAL_FREQ1 0xA7 #define VAL_FREQ0 0x62 #define VAL_MDMCFG4 0xF5 #define VAL_MDMCFG3 0x83 #define VAL_MDMCFG2 0x13 #define VAL_MDMCFG1 0x22 #define VAL_MDMCFG0 0xF8 #define VAL_DEVIATN 0x15 #define VAL_MCSM2 0x07 #define VAL_MCSM1 0x33 #define VAL_MCSM0 0x10 #define VAL_FOCCFG 0x16 #define VAL_BSCFG 0x6C #define VAL_AGCCTRL2 0x03 #define VAL_AGCCTRL1 0x40 #define VAL_AGCCTRL0 0x91 #define VAL_WOREVT1 0x80 #define VAL_WOREVT0 0x00 #define VAL_WORCTRL 0xFB #define VAL_FREND1 0x56 #define VAL_FREND0 0x10 #define VAL_FSCAL3 0xE9 #define VAL_FSCAL2 0x2A #define VAL_FSCAL1 0x00 #define VAL_FSCAL0 0x1F #define VAL_FSTEST 0x59 #define VAL_PTEST 0x7F #define VAL_AGCTEST 0x3F #define VAL_TEST2 0x81 #define VAL_TEST1 0x35 #define VAL_TEST0 0x09 #define VAL_PARTNUM 0x00 #define VAL_VERSION 0x06
However, upon transitioning the chip into the power-down state, I encountered a challenge where I am unable to receive any packets using the GDO02 pin for reception.
I seek your guidance on how to properly exit the power-down mode and successfully receive packets when they arrive.
Thank you for your assistance.