Tool/software:
Hi,
I am considering a migration to the CC1312PSIP using WB-DSSS 120kbps and DSSS = 1:2. I need to configure a SiLabs part to communicate with it for legacy reasons, but I can't find the details of the DSSS chipping code base and FEC.
Can you please answer the following:
1) What is the DSSS chipping code base for this mode?
2) What is the chipping code length?
3) What is the FEC 1:2? Is this the convolutional encoder?
Many thanks,
Andy
Hi,
Yes, I've read through this several times. I'm not understanding how DSSS is implemented here:
Do I have this correct? The data is fed through the convolutional encoder for forward error correction. Each data bit produces two encoded bits. This then goes to the DSSS 1:2 which takes each encoded bit and creates a two-bit symbol which is transmitted via the GFSK modulator.
Therefore each data bit is transmitted as four bits over the air. 1bit -> 2 FEC bits -> 4 DSSS bits.
And a '0' is changed to '00', and a '1' is changed to '11' by the DSSS?
It looks like my legacy chip DSSS cannot be configured to produce only two-bit symbols per data bit, but has to be 4-bit symbol presumably to 2 data bits. Does this mean the radios are not compatible with this PHY configuration?
Thanks for your help.
Hi Andrew,
when you look at the pipeline the data bits are first fed through the Convolutional Encoder. That already encodes each data bit to two encoded bits.
Following these two encoded bits are input to the Direct Sequence spreader. Depending on the selected dsss mode it either transmits them as they are or further encodes them with the maximum dsss encoding each encoded bit to 8 encoded bits that will be transmitted.
If you want now to encode 2 data bits to a 4 -bit symbol you would need to use dsss mode 2.
Please let me know if you have further questions.
Kind regards,
Theo
Hi,
Thank you for your reply. My plan is to write the FEC encoder in firmware for the non-TI part for compatibility. Looking at the convolutional encoder, do you have any more information or help on implementing this in code? I am confused how the XOR operation works looking at the diagram. The whole point of this is to be able to use the CC1312PSIP module as it is FCC compliant and this is the part that I need to get working so we can move to the module and maintain compatibility with older products.
Is there a way to output the convolutional encoder output data stream to a gpio?
Thank you,
I think this online calculator looks like the same encoder. Can you confirm?
Hi,
Thank you, this is helpful. I can write some software to produce the convolutional encoded data from the transmit side, (I don't actually need to decode it), but for now I am trying to communicate with the CC1312PSIP using WB-DSSS 1:1 mode using preconfigured data. I need a bit more information on the FEC and the DSSS (even though it's set to not create any samples).
Answering the following would be extremely helpful:
1) Assuming the FEC starts off loaded with zeros, are these three zeros actually transmitted?
2) The FEC will be flushed at the end too, are these zeros transmitted?
It would be very helpful to know for example, how a payload of 0xAA is transmitted. According to the online calculator: 0xAA produces the encoded data:
1 1 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1 0 0
which includes the leading zeros but no ending zeros.
3) Finally, the DSSS documentation states that there are termination bits. What are these exactly?
In summary, it would be really helpful to know how an example byte of data is transmitted when using the WB-DSSS 1:1 for example.
Alternatively, it would be helpful to know that what I am trying to do is not possible.
Many thanks for your help,
Andy
