Tool/software:
Hello,
While reading the CC113L datasheet (section 5.13.1.2 Manual Reset), I noticed a possible inconsistency between the description and Figure 5-13.
The text says:
“When SO goes low again, reset is complete and the chip is in the IDLE state.”
But in Figure 5-13 (Power-On Reset with SRES), SO goes low once when CSn is pulled low (CHIP_RDYn), then goes high during the oscillator stabilization. At the end of the figure, SO remains high, while according to the text it should go low again to signal the end of reset.
So my question is:
Is the figure simplified (and the final transition of SO back to low is missing)?
Or does SO should stay high after SRES strobe ?
Thanks in advance for your clarification.
