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CC113L and CC115L recieve problem

Other Parts Discussed in Thread: CC115L, CC113L, TEST2, CC110L

Hello everybody. Im so much new on this topic. I started firstly to send packets with CC115L and its ok I can send and I can read from SmartRF correctly. my question about CC113L and recieving data. I couldnt do it yet. I did config registers same with SmartRF. but I cant read.Im sending only 1 byte for test. Im using pic16f1824 for test. I need help

Thank you

  • Hi

    Hi

    Please see the code examples for how to send and receive packets. This code example is for an MSP430 MCU so you must port the code to PIC controller you are using.

    It is always a good idea to test your code on known good HW (our EM boards) before testing on your own HW. This way it is easier to know if the problem is SW or HW related.

    BR

    Siri

  • Hi,

    I sent correctly byte(s) and read in SmartRF very well.. just I need to know reading..like firstly send rx address and after CC113L will send me 1 byte of data or how ? I need to know it good. and where is this code examples ?

    Thank you

  • Hi

    Here is the code example: 3056.cc110L_easy_link_msp_exp430g2.zip

    You strobe RX, wait for the packet received signal is asserted (falling edge of GDOx, when IOOCFGx = 0x06) and then you read the packet from the RX FIFO.

    Siri

  • Hello,

    I tried so many thing again but GDO2 pin is not changing.. Im sending 0x54 data from CC115L and if I can read I will rise up BUZZER.. where is my problem please help me.

    here is code ;



    #include <stdio.h>
    #include <xc.h>
    #include <stdlib.h>
    #include "MCUConfig.h"
    #include "MCUInit.h"
    #include <delays.h>
    #include <pic16f1824.h>
    #include <eeprom_routines.h>

    void setup_rf()
    {
        CS=0;
        _delay(20);
        spi_transfer(0x36);
        spi_transfer(IOCFG2);    spi_transfer(0x06);
        spi_transfer(IOCFG1);    spi_transfer(0x06);
        spi_transfer(IOCFG0);    spi_transfer(0x06);
        spi_transfer(FIFOTHR);   spi_transfer(0x00);
        spi_transfer(SYNC1);     spi_transfer(0xd3);
        spi_transfer(SYNC0);     spi_transfer(0x91);
        spi_transfer(PKTLEN);    spi_transfer(0x01);
        spi_transfer(PKTCTRL0);  spi_transfer(0x04);
        spi_transfer(PKTCTRL1);  spi_transfer(0x04);
        spi_transfer(ADDR);      spi_transfer(0x00);
        spi_transfer(CHANNR);    spi_transfer(0x00);
        spi_transfer(FSCTRL1);   spi_transfer(0x06);
        spi_transfer(FSCTRL0);   spi_transfer(0x00);
        spi_transfer(FREQ2);     spi_transfer(0x21);
        spi_transfer(FREQ1);     spi_transfer(0x62);
        spi_transfer(FREQ0);     spi_transfer(0x76);
        spi_transfer(MDMCFG4);   spi_transfer(0xf5);
        spi_transfer(MDMCFG3);   spi_transfer(0x83);
        spi_transfer(MDMCFG2);   spi_transfer(0x43);
        spi_transfer(MDMCFG1);   spi_transfer(0x22);
        spi_transfer(MDMCFG0);   spi_transfer(0xf8);
        spi_transfer(DEVIATN);   spi_transfer(0x15);
        spi_transfer(MCSM2);     spi_transfer(0x07);
        spi_transfer(MCSM1);     spi_transfer(0x30);
        spi_transfer(MCSM0);     spi_transfer(0x28);
        spi_transfer(FOCCFG);    spi_transfer(0x16);
        spi_transfer(BSCFG);     spi_transfer(0x6c);
        spi_transfer(AGCCTRL2);  spi_transfer(0x03);
        spi_transfer(AGCCTRL1);  spi_transfer(0x40);
        spi_transfer(AGCCTRL0);  spi_transfer(0x41);
        spi_transfer(FREND1);    spi_transfer(0x56);
        spi_transfer(FREND0);    spi_transfer(0x10);
        spi_transfer(FSCAL3);    spi_transfer(0xe9);
        spi_transfer(FSCAL2);    spi_transfer(0x2a);
        spi_transfer(FSCAL1);    spi_transfer(0x00);
        spi_transfer(FSCAL0);    spi_transfer(0x1f);
        spi_transfer(TEST2);     spi_transfer(0x81);
        spi_transfer(TEST1);     spi_transfer(0x35);
        spi_transfer(TEST0);     spi_transfer(0x09);
        CS=1;
    }
    void main() {
        MCUinit();
        spi_setup();
        setup_rf();
        SDO=0;
        spi_transfer(SRX);
        char data;
        while(1)
        {
            LED=GDO2;
            if(BUTON1==0)
            {
              LED=1;
              CS=0;
              spi_transfer(RXFIFO);
              spi_transfer(NOP);//nop
              CS=1;
              data=SSP1BUF;

              //eeprom_write(0x00,gelen);
              if(data==0x54)
              {
                  BUZZER=1;
              }
              while(BUTON1==0);
              LED=0;
              spi_transfer(SRX);
            }
                      
        }
        
    }


  • I think I coudlnt explain very well,

    Just I need some informations. Im not using msp430 thats why I couldnt use library. in pic I must know how I can read. like ;

    Send SRX,

    Send RX FIFO,

    Send some NOP for make clock for SPI and read return data.

    etc....

    I dont know how I should do it. in my code I was waiting for 0x54 data and if it come Im opening buzzer for signal.. from transmitter Im sending 0x54 already. in this point I lost so much time and really I need to solve this problem for my project. Please help me its so much important.

  • You must do the following:

    Strobe SRX

    Wait for a falling edge on the GDOx signal (IOCFGx  =0x06)

    Send the RXFIFO address on the SPI (the burst bit must be asserted if you are going to read more than 1 byte)

    Transmit a dummy byte out on the MOSI line to be able to clock read back data.

    It is not possible to go into details on how you should do this as that depends on how the SPI interface on your MCU works.

    You must use a scope to confirm that your SPI works according to spec.

    BR

    Siri

  • I did like you told. IOCFG2=0x06 but GDO2 pin is not changing never always its in low. Im checking by scope. SPI sends data like I want its ok. just GDO2 pin is not chaning. and also when I sent RXFIFO address and after NOP as dummy always coming back different data from CC113L which I didnt send.

    Thank you

  • If you do not get an interrupt on GDO2 that means that there are no data being received, which again means that you should not read the RXFIFO (This is stated in the data sheet).

    I would assume that your problem is HW related. To confirm this you should first run your code on our HW by connecting your MCU to our Ems to see that you are able to get this to work. When this works you can try to find out what is wrong with your HW.

    Br

    Siri

  • Have you remembered to configure the output power on your transmitter (PATABLE)??

    Siri

  • Yes of course. Transmitter is work good because I can read from SmartRF data which I sent. even from SmartRF(connected TRxEB ) Im sending but reciever still same.

  • Hello again,

    I checked many things and finally GDO2 is high when data came. but I couldnt read correct data yet. always different data is coming.

  • Hi

    Are you using radio settings exported from SmartRF Studio and are you waiting for the complete packet to be received (falling edge of GDOx, where IOCFGx = 0x06) before you start reading the FIFO?

    When you are reading the FIFO, how many bytes are you reading?

    If you are using variable packet length and the first byte received after sync is 3, there will be in total 6 bytes in the FIFO (if append status = 1). You will have the length byte, 3 payload bytes and 2 status bytes. If you only read the length and the payload bytes there will be two bytes left in the FIFO and these will be the two first bytes you read next time you access the FIFO.

    When using variable packet length mode you should always read NUM_RXBYTES or read the length byte to find out how many bytes are in the FIFO.

    If you are using fixed packet length mode the radio will receive as many bytes as configured through the PKTLEN register. If PKTLEN = 1, there will be 3 bytes in the FIFO when a packet is received (1 payload byte and 2 status bytes).

    Remember to use maximum length filtering when using variable packet length mode to avoid RRXFIFO OVERFLOW.

    BR

    Siri

  • Hi,

    Im using fixed packet lenght mode and PKTLEN=0x01 here is configuration;


    TX;

    CS=0;
        _delay(60);
        spi_transfer(0x36);

        spi_transfer(IOCFG2);    spi_transfer(0x2e);
        spi_transfer(IOCFG1);    spi_transfer(0x2e);
        spi_transfer(IOCFG0);    spi_transfer(0x06);
        spi_transfer(FIFOTHR);   spi_transfer(0x00);
        spi_transfer(SYNC1);     spi_transfer(0xd3);
        spi_transfer(SYNC0);     spi_transfer(0x91);
        spi_transfer(PKTLEN);    spi_transfer(0x01);
        spi_transfer(PKTCTRL0);  spi_transfer(0x04);
        spi_transfer(CHANNR);    spi_transfer(0x00);
        spi_transfer(FSCTRL0);   spi_transfer(0x00);
        spi_transfer(FREQ2);     spi_transfer(0x21);
        spi_transfer(FREQ1);     spi_transfer(0x62);
        spi_transfer(FREQ0);     spi_transfer(0x76);
        spi_transfer(MDMCFG4);   spi_transfer(0xf5);
        spi_transfer(MDMCFG3);   spi_transfer(0x83);
        spi_transfer(MDMCFG2);   spi_transfer(0x43);
        spi_transfer(MDMCFG1);   spi_transfer(0x22);
        spi_transfer(MDMCFG0);   spi_transfer(0xf8);
        spi_transfer(DEVIATN);   spi_transfer(0x15);
        spi_transfer(MCSM1);     spi_transfer(0x30);
        spi_transfer(MCSM0);     spi_transfer(0x28);
        spi_transfer(0x20);      spi_transfer(0xfb);
        spi_transfer(FREND0);    spi_transfer(0x10);
        spi_transfer(FSCAL3);    spi_transfer(0xe9);
        spi_transfer(FSCAL2);    spi_transfer(0x2a);
        spi_transfer(FSCAL1);    spi_transfer(0x00);
        spi_transfer(FSCAL0);    spi_transfer(0x1f);
        spi_transfer(PATABLE);   spi_transfer(0x5C);
        CS=1;


    RX;

      SPIWriteReg(IOCFG2,   0x06); // GDO2 output pin config.
        SPIWriteReg(IOCFG0,   0x06); // GDO0 output pin config.
        SPIWriteReg(PKTLEN,   0x01); // Packet length.
        SPIWriteReg(PKTCTRL1, 0x04); // Packet automation control.
        SPIWriteReg(PKTCTRL0, 0x04); // Packet automation control.
        SPIWriteReg(ADDR,     0x00); // Device address.
        SPIWriteReg(CHANNR,   0x00); // Channel number.
        SPIWriteReg(FSCTRL1,  0x06); // Freq synthesizer control.
        SPIWriteReg(FSCTRL0,  0x01); // Freq synthesizer control.
        SPIWriteReg(FREQ2,    0x21); // Freq control word, high byte
        SPIWriteReg(FREQ1,    0x62); // Freq control word, mid byte.
        SPIWriteReg(FREQ0,    0x76); // Freq control word, low byte.
        SPIWriteReg(MDMCFG4,  0xF5); // Modem configuration.
        SPIWriteReg(MDMCFG3,  0x83); // Modem configuration.
        SPIWriteReg(MDMCFG2,  0x43); // Modem configuration.
        SPIWriteReg(MDMCFG1,  0x22); // Modem configuration.
        SPIWriteReg(MDMCFG0,  0xF8); // Modem configuration.
        SPIWriteReg(DEVIATN,  0x00); // Modem dev (when FSK mod en)
        SPIWriteReg(MCSM1 ,   0x3F); //MainRadio Cntrl State Machine
        SPIWriteReg(MCSM0 ,   0x18); //MainRadio Cntrl State Machine
        SPIWriteReg(FOCCFG,   0x1D); // Freq Offset Compens. Config
        SPIWriteReg(BSCFG,    0x1C); //  Bit synchronization config.
        SPIWriteReg(AGCCTRL2, 0xC7); // AGC control.
        SPIWriteReg(AGCCTRL1, 0x00); // AGC control.
        SPIWriteReg(AGCCTRL0, 0xB2); // AGC control.
        SPIWriteReg(FREND1,   0xB6); // Front end RX configuration.
        SPIWriteReg(FREND0,   0x10); // Front end RX configuration.
        SPIWriteReg(FSCAL3,   0xE9); // Frequency synthesizer cal.
        SPIWriteReg(FSCAL2,   0x2A); // Frequency synthesizer cal.
        SPIWriteReg(FSCAL1,   0x00); // Frequency synthesizer cal.
        SPIWriteReg(FSCAL0,   0x1f); // Frequency synthesizer cal.
        SPIWriteReg(FSTEST,   0x59); // Frequency synthesizer cal.
        SPIWriteReg(TEST2,    0x88); // Various test settings.
        SPIWriteReg(TEST1,    0x31); // Various test settings.
        SPIWriteReg(TEST0,    0x0B); // Various test settings.
        SPIWriteReg(SYNC1,    0xd3);
        SPIWriteReg(SYNC0,    0x91);


    and when Im reading Im waiting GDO2. when GDO2 is high Im starting read after some little delay. Im sending 1 byte and Im trying read 1 byte.

  • Start by changing MCSM0 to 0x18 instead of 0x28. If not, the first packet sent after power-up will never be at the correct frequency since calibration happens after the packet is sent. If you want to keep 0x28, you must do a manual calibration at start-up.

    You must wait for a falling edge of GDO2 before reading the FIFO and you must read 3 bytes and not 1 as you have APEEND_STATUS in PKTCTRL1 = 1.

    If you set PKTCTRL1 = 0x00 you can read only 1 byte after a falling edge of GDO2.

    Siri

  • FinallyI have correct packet :)

    just not each time..5 sent data 1 is correct.I think it again because of register config ?

  • Hi

    It can either be register settings (please start by testing with one of the typical settings from SmartRF Studio and the change the registers when you have a stable link) or it can be your HW.

    It is always a good idea to test your register settings and SW on our Ems first and then, when everything works as expected, you can start testing on your own HW.

    BR

    Siri

  • Hello again :)

    Im sending 17 bytes and Im reading now in my own HW. just there is little problem. Im sending 17 bytes first time and reciever is reading something totally different..when I try second time it read perfect. after Im sending different 17 bytes..and again reciever reading previous 17 bytes in first reading..and in second reading again correct. I think something missing like flush rxfifo. but I put in code already.after reading fifo must be empty but its not. where is problem ?

  • Hi

    If you are using variable packet length mode and you transmit 17 bytes, you must write the length byte (16) and then 16 bytes to the TX FIFO. On the receiver side you will have 19 bytes in the RXFIFO (length byte + 16 payload bytes + 2 status bytes). You must read all 19 bytes for the FIFO to empty. If you have read the complete packet there is no need to flush the FIFO. Remember that the radio can receive noise as well. It is therefore not sure that all packets received are the packets you sent. When you get a packet received interrupt you should therefore always check how many bytes are in the FIFO before starting to read it.

    Siri

  • Hi,

    Im using fixed packet length and in PKTLEN=0x11 for 17 bytes.. should I change it ? and about packet count. How I can learn it ? by which command or strobe?

    thanks,

  • Fixed packet length is OK. Then you know that every time you receive a packet (falling edge on GPIOx when IOCFGx = 0x06) there is 17 bytes in the FIFO (19 if APPEND_STATUS = 1). Make sure that you do not read the RXFIFO before the complete packet is received (falling edge and not rising edge of the packet received signal)

    Siri

  • Hi,

    My configuration for IOCFG2=0x06 and Im waiting in my code till GDO2==1 and after Im reading. APPEND_STATUS=0 so I must read 17 bytes yes ? but always there is 1 more byte before my packets.I must read 1+17 bytes..and also there is this FIFO flush problem still

  • You are reading the FIFO too early. When the GDO2 becomes 1 it only means that sync is received but nothing is put in the FIFO yet. When you read an empty FIFO you mess up the FIFO pointers. You must wait for GDO2 to become 1 and then 0 again (falling edge on GDO2) before the complete packet is in the FIFO.

    Siri

  • Hi,

    Thank you so much, now everything is perfect :)

    finally it works.

  • Hello again,

    I have a problem . After 15-19 data sending CC110L is not working anymore till I shut off power and give again. What do you think about it ?

  • Is it the transmitter who is not sending or the receiver that is not receiving? What state (MARCSTATE) is the radio in when it stops working?

    Without more knowledge of your code and what fails it is kind of difficult to come with suggestions.

    Siri

  • Reciever is stopping. I didnt check MARCSTATE I fixed it by go into RXMode after every packge recieving. But I dont know it good way.