Could a TI engineer shed some light on how the system clock is synchronized with the divided clock in the timer modules? I have an application dictated necessity to synchronize the compare outputs on two different timers operating at different clock divisors. Essentially, I need to run synchronized PWM on many output channels, and due to battery constraints, need to guarantee the outputs are mutually exclusive.
A little information about the clocking architecture could help me achieve this. For example, are the different divisor clocks derived from a single clock divider, or are they independent per timer? When does the divider start ticking relative to the system clock -- is an enable latched when the timer enable is first set, or is some other mechanism used?
If I set the enable bits for each timer in back to back assembly instructions, will that guarantee the timers are sync'd within 1-2 system clocks? Or will the enable outputs be synchronized into the divided clock domain, and thus subject to a delay until the next divided clock tick? In the later case is it possible to monitor the state of the divided clock, so that I may set enables when both clocks are in the desired start state?