Hi,
I have three questions regarding CC1190:
1. The datasheet says
"The output power can be reduced by setting the pin HGM low. If a reduced maximum output power is wanted, theimpedance seen by the PA should be increased, thus increasing the PA efficiency by changing the outputmatching network."
We would like to have an output power in range of 18-23 dBm. Where and how much I am supposed to increase the impedance? My first guess is to increase value of the L21. We use the 869.4-869.65 MHz range.
2. On the block diagram the PA_EN, LNA_EN and HGM are going in a box labelled "Logic". Does it completely take care to exclude a state where both PA_EN and LNA_EN are enabled? My idea is to control the GDO2 of the CC110L by setting its level by SPI commands and using a single FET to ensure opposite levels on the pins.
TX: PA=1, LNA_EN=0, HGM=0
RX: PA=0, LNA_EN=1, HGM=1 - to ensure better sensitivity thus enabling lower power on the TX counterpart.
I am aware a FET will introduce a short delay/overlap on level changes. Will "Logic" ensure ample time between the TX->RX / RX->TX transitions? I took it for granted since I couldn't find any constraints on timing between level changes or overlaps in the datasheet.
Does it have any importance at all, if during transitions the TX of the CC110x is always off? As there is no input signal to the CC1190 there should be no RF output to propagate to LNA_IN pin and damaging the LNA.
3. According to the data sheet if HGM=1 one should expect a gain of +26-27dB in TX. What is the TX power added when HGM=0?
There are two rows in the datasheet for PIN = -20 dBm and for HGM=1/0 stating the gain being 27.9 and 24.6 respectively (Vcc, frequency, temperature may vary them of course). Will HGM=1 just add another 3dB to the TX or there is more behind?
Will therefore HGM=0 fit our needs better by enabling us to use higher input power as recommended in "Controlling the Output Power from CC1190" on page 8?
Thanks,
Akos
