CC110L : Idle after RX when more than 271 packets received instead of staying in RX

The calibration has nothing to do with it. If the PLL was out of lock you would simply not receive any more packets, but the radio would still be in RX state (CC110L cannot change state based on being in lock or not).

When RXOFF_MODE is RX the radio will never leave RX mode if the FIFO does not overflow. In an overflow condition the radio will enter RX_OVERFLOW state (and not IDLE).

How do you know that your radio is in IDLE state? Do you read MARCSTATE after it fails or do you just assume so since you are not able to receive anymore?

You can also run into the RXFIFO_OVERFLOW issue described in the CC110L errata note. You will then be stuck in RX state but you will not be able to receive any data.

Siri

Hi Siri,

Thanks for the answer. Yes, I read marcstate after it fails. I was surprised that the state was Idle instead of RXOverflow.

Do you confirm that only an SIDLE or SFRX command can change the state from RXOverflow to Idle?

One question about the errata, if the CC110L is stuck in RX instead of RXOverflow, does the pin configured in  0x06 will notice an RXOverflow?

Thank you

Yes I can. If the radio is stuck in RX, the GPIO configured as sync received (0x06) will stay high adn not de-assert.

Is the problems you are seeing on our TrxEBs. If they are you can send me your IAR workspace (does not need you r complete application, just an example where the radio is in RX receiving packets until it fails).

I can then try to debug your code to see where the problems might be.

BR

Siri

Hi,

It's a Renesas HEW project.

Here is the Read function :

void Drv_Cc110l_Read(void* arg, uint8 *rxData, uint8 *len)
{
	marcstate_e cc110lState;
	uint8 rxBytesVerify, rxBytes;
	
	*len = 0x00; //Return 0x00 size if no read
	
	if(presenceRFCard && ((cc110lStatus & DRV_CC110L_STATE_OPENED) == DRV_CC110L_STATE_OPENED))
	{
		if(cc110LRadioTxRx != CC110L_STATE_RX)
		{
			irqGenerated = FALSE;
			Drv_cc110l_Change_Mode(state_rx); //idle + flush RX FIFO + RX
		}
		else 
		{
			if(irqGenerated == TRUE)
			{
				irqGenerated = FALSE;
				cc110lState = Drv_cc110l_Get_Status();
				if(state_rx_ovf == cc110lState)
				{
					Drv_cc110l_Change_Mode(state_rx); //idle + flush RX FIFO + RX
				}
				else
				{
					// The RXBYTES register must read the same value twice
					// in a row to guarantee an accurate value
					cc11xLSpiReadReg(CC110L_RXBYTES,&rxBytesVerify,1);
					do
					{
						rxBytes = rxBytesVerify;
						cc11xLSpiReadReg(CC110L_RXBYTES,&rxBytesVerify,1);
					}
					while(rxBytes != rxBytesVerify);
					// The RX FIFO is not empty, process contents
			    	        cc11xLSpiReadRxFifo(len, 1);
					if((rxBytes == ((*len) + 3)) && ((rxBytes & 0x80) != 0x80)) // We don't have a FIFO error condition -> get packet
					{
						*rxData = *len;
						rxData++;
						*len += 2; //inclu CRC + RSSI
						cc11xLSpiReadRxFifo(rxData, *len);
					}
					else
					{
						Drv_cc110l_Change_Mode(state_rx); //idle + flush RX FIFO + RX
					}
				}
			}
		}
	}	
}

Here is the IRQ function linked to the 0x06 CC110L pin:

#pragma interrupt (Excep_IRQ12(vect=VECT_ICU_IRQ12))
void Excep_IRQ12(void)
{	
	irqGenerated = TRUE;
	if(IR(ICU, IRQ12) == 0x01)
	{
		IR(ICU, IRQ12) = 0x00; //Clear IR flag
	}
}

BR

Pierre

Hi Pierre

I have looked at your code and have some questions.

// The RXBYTES register must read the same value twice in a row to guarantee an accurate value cc11xLSpiReadReg(CC110L_RXBYTES,&rxBytesVerify,1);

do {

    rxBytes = rxBytesVerify;

    cc11xLSpiReadReg(CC110L_RXBYTES,&rxBytesVerify,1);

} while(rxBytes != rxBytesVerify);

// The RX FIFO is not empty, process contents

cc11xLSpiReadRxFifo(len, 1);

How can you know that your RXFIFO is not empty?

You are only checking that rxBytes and rxcBytesVerify are identical but you are not checking that they are not 0. 

Trying to read an empty FIFO will cause problems.

Change the code so that you only read the FIFO if rxBytes != 0 and also use packet filtering (set PKTLEN = 61 to avoid the bug described in the errata note)

BR

Siri

Hi Siri,

Thanks for your answer. I already have PKTLEN = 61. I added the correction with rxBytes > 0x00 (I read the RX Fifo only if rxBytes > 0x00), but the issue is still here. After 271 packets received, CC110L goes to IDLE.

BR

Pierre

Here is my configuration :

static const registerSetting_t cc110LmediumDataRateRfSettings[] = {
    {CC110L_PKTCTRL1  ,0x0C},  /* PKTCTRL1      Packet Automation Control                      */
    {CC110L_ADDR      ,0x00},  /* ADDR          Device Address                                 */
    {CC110L_FSCTRL1   ,0x06},  /* FSCTRL1       Frequency Synthesizer Control                  */
    {CC11xL_FSCTRL0   ,0x00},  /* FSCTRL0       Frequency Synthesizer Control                  */
    {CC11xL_MDMCFG4   ,0x9A},  /* MDMCFG4       Modem Configuration                            */
    {CC11xL_MDMCFG3   ,0x83},  /* MDMCFG3       Modem Configuration                            */
    {CC11xL_MDMCFG2   ,0x93},  /* MDMCFG2       Modem Configuration                            */
    {CC110L_MDMCFG1   ,0x22},  /* MDMCFG1       Modem Configuration                            */
    {CC11xL_DEVIATN   ,0x35},  /* DEVIATN       Modem Deviation Setting                        */
    {CC110L_MCSM2     ,0x03},  /* MCSM2         Main Radio Control State Machine Configuration */
    {CC110L_FOCCFG    ,0x16},  /* FOCCFG        Frequency Offset Compensation Configuration    */
    {CC110L_BSCFG     ,0x6C},  /* BSCFG         Bit Synchronization Configuration              */
    {CC110L_AGCCTRL2  ,0x43},  /* AGCCTRL2      AGC Control                                    */
    {CC110L_AGCCTRL1  ,0x40},  /* AGCCTRL1      AGC Control                                    */
    {CC110L_AGCCTRL0  ,0x91},  /* AGCCTRL0      AGC Control                                    */
    {CC110L_RESERVED_0X20,0xFB},  /*RESERVED_0X20    Reserved register                         */
    {CC110L_FREND1    ,0xB6},  /* FREND1        Front End RX Configuration                     */
    {CC110L_FREND0    ,0x10},  /* FREND0        Front End TX Configuration                     */
    {CC11xL_TEST2     ,0x81},  /* TEST2         Various Test Settings                          */
    {CC11xL_TEST1     ,0x35},  /* TEST1         Various Test Settings                          */
    {CC11xL_TEST0     ,0x09}   /* TEST0         Various Test Settings                          */
};
/* Common register settings for CC11xL radios and test case*/
static const registerSetting_t commonRfSettings[] = {
    {CC11xL_IOCFG2        ,0x09},  /* IOCFG2          GDO2 Output Pin Configuration                   */
    {CC11xL_IOCFG1        ,0x2E},  /* IOCFG1          GDO1 Output Pin Configuration                   */
    {CC11xL_IOCFG0        ,0x06},  /* IOCFG0          GDO0 Output Pin Configuration                   */
    {CC11xL_FIFOTHR       ,0x07},  /* FIFOTHR         RX FIFO and TX FIFO Thresholds (Ingored)        */
    {CC11xL_SYNC1         ,0xD3},  /* SYNC1           Sync Word, High Byte                            */
    {CC11xL_SYNC0         ,0x91},  /* SYNC0           Sync Word, Low Byte                             */
    {CC11xL_PKTLEN        ,0x3D},  /* PKTLEN          Packet Length                                   */
    {CC11xL_PKTCTRL0      ,0x05},  /* PKTCTRL0        Packet Automation Control                       */
    {CC11xL_FREQ2         ,0x21},  /* FREQ2           Frequency Control Word, High Byte               */
    {CC11xL_FREQ1         ,0x62},  /* FREQ1           Frequency Control Word, Middle Byte             */
    {CC11xL_FREQ0         ,0x76},  /* FREQ0           Frequency Control Word, Low Byte                */
    {CC11xL_MCSM1         ,0x3C},  /* MCSM1           Main Radio Control State Machine Configuration  */
    {CC11xL_MCSM0         ,0x18},  /* MCSM0           Main Radio Control State Machine Configuration  */
    {CC11xL_FSCAL3        ,0xEA},  /* FSCAL3          Frequency Synthesizer Calibration               */
    {CC11xL_FSCAL2        ,0x2A},  /* FSCAL2          Frequency Synthesizer Calibration               */
    {CC11xL_FSCAL1        ,0x00},  /* FSCAL1          Frequency Synthesizer Calibration               */
    {CC11xL_FSCAL0        ,0x1F},  /* FSCAL0          Frequency Synthesizer Calibration               */
    {CC11xL_RESERVED_0X29 ,0x59},  /* RESERVED_0X29   Reserved register                               */
    {CC11xL_RESERVED_0X2A ,0x7F},  /* RESERVED_0X2A   Reserved register                               */
    {CC11xL_RESERVED_0X2B ,0x3F},  /* RESERVED_0X2B   Reserved register                               */
};

Hi Pierre

Glad to hear that the issue has been solved.

It is not a problem to read the RXFIFO while receiving a second packet as long as SW keeps track of which data belong to which packet and that you read the FIFO fast enough to make room for the second packet.

Siri