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Is there a particular reason for using 47nF decoupling capacitors in the CC1200 868Mhz reference design?

Other Parts Discussed in Thread: CC1200

Is it possible to replace them with 100nF (0402) caps? I couldn't find any information about the choice of decoupling capacitors in the datasheet.

Regards,

Yann

  • We have only tested the ref design using 47 nF decoupling capacitors. That said, I do not believe the value to be critical and 100 nF can be used instead. 

  • Just to be on the safe side: This is true for AVDD_x pins. On DCPL_x pins the value given in the ref design should be used.

  • Hi, I need to warm up that subject.  Not because 47nF is too exotic or too expensive, but because the situation is a bit funny.

    Design engineers would appreciate a bit more information than the comment: "use the values defined in the reference design". There are some of us out there who do not trust reference designs - partly because some of those designs are different from the use case the designer need to use the chip in sometimes and partly because many ref designs have been of less than reasonable quality (also from TI).

    If you care even a little of TI's reputation (that to my best knowledge is quite good), you should avoid degradfing documentation quality to drop to a level of some cheap chip manufacturers. Defining at least something about EVERY external component needed in a design is a must for a respectable company. TI does not share the silicon design and packaging info with the users and the users are not psychic (but many of us have more experience than you guys in tech support - no offense).

    Sadly this is already about 5th case of TI's poor documentation I have come across lately. And it does irritate.

    So, to cut my long story a bit shorter:

    if you possess any information why the DCPL_x pins should have exactly the values (and then I presume also Mfr/Mfr PN also) used in the ref design, do please explain. I actually need to minimize number of components on a bigger design and need to know asap.

    Thanks in advance!

  • The CC1200 has a number of LDOs internally. Some of them with an internal de-coupling cap and some with an external cap. The DCPL_x pins are the connection pins for external caps for the last group of LDOs. 

    The sizes of the decoupling caps on the DCPL_x pins are a tradeoff from the LDO designer. Changing the value will increase/ decrease the phase margin of the LDO and also impact other design parameters. Btw, I designed the ADC in the Rx path on CC1200 so I have a fairly good overview over the inner working of the chip also.

    Please let us know when you find items than should be documented better. It's not always easy to change the documentation but if it's covered on E2E it's possible to find later for others with the same question.

  • Hi again,

    thanks for the quick feedback. It is good to know that people answering questions in E2E are actual design engineers :)

    I do appreciate the fact that changing the capacitance will have an effect on the phase margin and increasing capacitance will bring down the pole frequency. At the same time I am sure that the capacitor is selected to have acceptable ripple voltage. So decreasing capacitance will result in increased noise... However I would hope that a 20% change of capacitance will not result in an instable solution!? Currently I do not know, I only make educated guesses as this is not defined.

    I believe that it would be not just a good idea, but quite needed for your customers to know a little about how they should use the chip i.e. all perpiherals that are a "must" and are considered as a part of the IC should have requirements specified in a clear manner. This also applies to all pins: some basics should be defined. I cannot imagine a design engineer that would not appreciate this.

    But the CC1200 the datasheet literally does not state anything about those decoupling caps. The CC1200 web page does not list the reference schematic directly. I am sure that you (designers) test all functional blocks of a new IC several times during prototyping and also the end product. Why on earth would you not put the findings in the datasheet? I do think that the phase graphs would answer the question. Alternatively, you could test and define a safe are of operation: for example

    MIN 33nF  - TYP 47nF - MAX 68nF, 

    and state that the designer has to take into account tolerance, dC over temperature, DC bias etc.

    Yes, this is an extra effort , but please try to undestand that your customers do not have any background info on the internals of the IC so even if they wanted to, it would be much bigger task for them. And multiply this effort by the number of customers using this IC (or at least 20% of the customers - the bigger the manufacturing QTYs the greater the pressure is to optimize the whole design)...

  • The number of simulations that has to be run doing design is very high and in many cases it's not practical to add more degree of freedom than required. To simulate what would happen if an external cap size is changed will add days/ weeks to the development phase. The same if we would to test it afterwards, it adds weeks to an already tight schedule so even though it could be practical for some customers to have a range to choose from given external components it's way to time consuming. It's not possible t know the consequence of a change component value without sims/ testing, hence the statement "follow the ref design". 47 nF is in the E12 series which should be easy to get access to.