CC1120 has empty RX FIFO after sync word interrupts

Hi

What register settings are you using? Have you enabled CRC filtering (FIFO_CFG.CRC_AUTOFLUSH = 1)? If so the radio will act as you described upon an CRC error.

No, I have CRC autoflush disabled. Here are my non-default settings:

{IOCFG3, 0, 0x57},
//GPIO3_INV = 0x01 = output inverted
//GPIO3_CFG = 0x17 = LNA_PA_REG_PD enabled
{IOCFG2, 0, 0x02},
//GPIO2_CFG = 0x02 = TXFIFO_THR enabled
{IOCFG0, 0, 0x06},
//GPIO0_CFG = 0x06 = PKT_SYNC_RXTX enabled
{SYNC_CFG1, 0, 0x07},
//SYNC_THR = 0x07 = sync word decision threshold (lower than default)
{SYNC_CFG0, 0, 0x15},
//SYNC_NUM_ERROR = 0x01 = check allows <2 bit errors in last received sync byte
{DCFILT_CFG, 0, 0x1C},
//DCFILT_FREEZE_COEFF = 0x00 = auto DC error compensation (by SmartRF Studio)
//DCFILT_BW_SETTLE = 0x03 = 256-sample DC filter settling period (by SmartRF Studio)
{PREAMBLE_CFG1, 0, 0x18},
//NUM_PREAMBLE = 0x06 = 4 preamble bytes
//PREAMBLE_WORD = 0x00 = 0xAA preamble byte
{MDMCFG0, 0, 0x05},
//TRANSPARENT_MODE_EN = 0x00 = transparent mode disabled
//DATA_FILTER_EN = 0x00 = transparent and extended data filters disabled (by SmartRF Studio)
{AGC_REF, 0, 0x20},
//AGC_REFERENCE = 0x20 = AGC reference level (by SmartRF Studio)
{AGC_CS_THR, 0, 0xE7},
//AGC_CS_THRESHOLD = -25 dBm carrier sense threshold
{AGC_GAIN_ADJUST, 0, 0x8C},
//GAIN_ADJUSTMENT = -116 dBm RSSI offset
//(measured RSSI1+GAIN_ADJUSTMENT = known signal strength)
{AGC_CFG3, 0, 0x11},
//RSSI_STEP_THR = 0x00 = 3 dB for step in RSSI
//AGC_ASK_BW = 0x00 = [-3 dB cutoff freq = 4*0.28*Rx Filter BW] (ASK/OOK only)
{AGC_CFG1, 0, 0xA9},
//AGC_SETTLE_WAIT = 0x01 = 32-sample wait time between AGC adjustments (by SmartRF Studio)
{AGC_CFG0, 0, 0xCF},
//RSSI_VALID_CNT = 0x03 = 9 estimates until RSSI update (by SmartRF Studio)
//AGC_ASK_DECAY = 0x03 = decay step of 5000 samples (ASK/OOK only)
{FIFO_CFG, 0, 0x78},
//CRC_AUTOFLUSH = 0x00 = disable flushing bad CRC packet from RX FIFO
//FIFO_THR = 0x78 = TX FIFO threshold is 120 bytes (6 bytes remaining in TX FIFO)
{SETTLING_CFG, 0, 0x03},
//FS_AUTOCAL = 0x00 = never auto-calibrate (use SCAL)
{FS_CFG, 0, 0x12},
//FS_LOCK_EN = 0x01 = out-of-lock detector enabled (by SmartRF Studio)
{PKT_CFG2, 0, 0x04},
//CCA_MODE = 0x01 = indicate clear channel with RSSI threshold
//PKT_FORMAT = 0x00 = normal FIFO mode
{PKT_CFG1, 0, 0x45},
//WHITE_DATA = 0x01 = data whitening enabled
//ADDR_CHECK_CFG = 0x00 = address check disabled
//CRC_CFG = 0x01 = CRC-16 (init ones) TX calculation and RX check enabled
//APPEND_STATUS = 0x01 = append 2 bytes (RSSI/LQI/PKT_CRC_OK) enabled
{PKT_CFG0, 0, 0x20},
//LENGTH_CONFIG = 0x01 = variable packet length (first byte after sync word)
{RFEND_CFG1, 0, 0x0E},
//RXOFF_MODE = 0x00 = enter Idle mode after receiving good packet
//RX_TIME_QUAL = 0x00 = exit RX mode if no packet is found before timeout
{RFEND_CFG0, 0, 0x00},
//TXOFF_MODE = 0x00 = enter Idle mode after sending packet
//TERM_ON_BAD_PACKET_EN = 0x00 = stay in Rx mode after receiving bad packet
{PA_CFG1, 0, 0x54},
//RAMP_SHAPE = 0x00 = 3/8 symbol ramp time, 1/32 symbol shape length (ASK/OOK only)
{PKT_LEN, 0, 0x7D},
//PACKET_LENGTH = 0x7D = 125-byte packet length check (2 status + 1 length)
{EXT_REG_SPACE, IF_MIX_CFG, 0x00},
{EXT_REG_SPACE, FREQOFF_CFG, 0x00},
//FOC_EN = 0x00 = freq. offset correction disabled
//(NOTE: not needed when freq. error is less than freq. deviation)
{EXT_REG_SPACE, FS_DIG1, 0x00},
{EXT_REG_SPACE, FS_DIG0, 0x5F},
//RX_LPF_BW = 0x03 = 170.8 kHz FS Rx loop bandwidth (by SmartRF Studio)
//TX_LPF_BW = 0x03 = 170.8 kHz FS Tx loop bandwidth (by SmartRF Studio)
{EXT_REG_SPACE, FS_CAL1, 0x40},
{EXT_REG_SPACE, FS_CAL0, 0x0E},
//LOCK_CFG = 0x03 = out-of-lock detector average time is infinite (by SmartRF Studio)
{EXT_REG_SPACE, FS_DIVTWO, 0x03},
{EXT_REG_SPACE, FS_DSM0, 0x33},
{EXT_REG_SPACE, FS_DVC0, 0x17},
{EXT_REG_SPACE, FS_PFD, 0x50},
{EXT_REG_SPACE, FS_PRE, 0x6E},
{EXT_REG_SPACE, FS_REG_DIV_CML, 0x14},
{EXT_REG_SPACE, FS_SPARE, 0xAC},
{EXT_REG_SPACE, FS_VCO0, 0xB4},
{EXT_REG_SPACE, XOSC5, 0x0E},
{EXT_REG_SPACE, XOSC1, 0x03}

I also use 2-FSK with DSSS. I'm looking into how often I perform FS calibration; is it possible that neglecting to do so before TX or RX may cause the behavior I've seen (sync word received but no RX FIFO filled)?

I confirmed that forcing FS calibration right before both TX and RX does not fix the issue I'm seeing.

Hi Tom

You are using variable packet length mode and set max packet length to 0x7D, meaning that you are using packet length filtering. If you receive a sync word, the PKT_SYNC_RXTX signal will be asserted. The length byte will then be checked and if the length is OK the packet is filled in the FIFO. If not, the packet is discarded and the PKT_SYNC_RXTX signal is de-asserted. When using any kind of filtering it is always necessary to check that there are data in the RX FIFO before trying to read it. This can be done by checking NUM_RXBYTES. One should never try to read an empty FIFO.

BR

Siri

I am reading the NUM_RXBYTES register first; then when it gives me 0, I skip reading the data bytes from RX_FIFO. I also haven't seen any problems with my packet length filtering usually (my specific packets under test are only 9 to 13 bytes long).

Since you get the interrupt when you are supposed to (when the transmitter is sending) an empty FIFO means that there was an error in the length byte since this is the only filtering you are using.

To confirm this you can configure your receiver for fixed packet length and always receive 13 bytes (if this is you max packet length). You can then analyze all the packets you are receiving and see if there is something in common with the packets that are failing.

BR

Siri

Unfortunately I was busy and unable to investigate this issue for awhile, and now that I've returned I can't reproduce it. I will update this thread if I manage to reproduce it and/or identify the cause.