Programming the transmitted power level in cc1101 in ASK/OOk mode

vignesh M S

Other Parts Discussed in Thread: CC1101

Hi all,

Is it possible to program the desired power levels for logic '0' and logic '1' in CC1101 / CC430 chip while operating in ASK/OOK mode. I observe that whatever transmitted power I set using PATABLE register corresponds to the logic '0' and -65 dBm power level always corresponds to logic '1' t the transmitter end.

Basically, I want to establish a wireless link between a custom-made transmitter setup and CC1101 based receiver setup in OOK modulation format operating in asynchronous mode. THe customized transmitter transmits two power levels with a diffeence of 20 dB. I want to know how the demodulator differentiates the two power levels i.e. is there any threshold power level that can be programmable for configuring the CC1101 receiver in OOK mode.

Thanks,

Vignesh

over 9 years ago

0 Sverre over 9 years ago

TI__Mastermind 39860 points

When transmitting in OOK mode PATABLE[0] defines the logic '0' level and PATABLE[1] the logic '1' level if you don't enable shaping. If shaping is enabled PATABLE[1:7] is used to shape each bit. Refer to section 25 in the cc1101 data sheet for details.

A modulation depth of 20 dB is ok for reception. You might need to tweak the OOK/ASK decision boundary through register AGCCTRL0.FILTER_LENGTH.

To find the optimum register settings for OOK operation please refer to design note DN022; www.ti.com/lit/SWRA215E

0 vignesh M S over 9 years ago in reply to Sverre

Expert 1180 points

Hi,

Thanks for the reply. I was successfully able to program the transmitted power levels and there is no issue with the OOK transmitter. I can observe two programmed power levels when sending 0's and 1's. But the data being demodulated at the receiver has a lot of errors. Please find the register settings below:

TRANSMITTER REGISTER SETTINGS:

#define IOCFG2_VAL 0x2E  // IOCFG2        GDO2 Output Pin Configuration-
#define IOCFG1_VAL 0x2E  // IOCFG1        GDO1 Output Pin Configuration
#define IOCFG0_VAL 0x2D  // IOCFG0        GDO0 Output Pin Configuration-
#define FIFOTHR_VAL 0x47   // FIFOTHR       RX FIFO and TX FIFO Thresholds
#define SYNC1_VAL   0xD3   // SYNC1         Sync Word  High Byte
#define SYNC0_VAL    0x91   // SYNC0         Sync Word  Low Byte
#define PKTLEN_VAL   0xFF   // PKTLEN        Packet Length-
#define PKTCTRL1_VAL   0x00   // PKTCTRL1   0x04   Packet Automation Control-
#define PKTCTRL0_VAL   0x32   // PKTCTRL0   0x05 for variable pkt mode  Packet Automation Control-
#define ADDR_VAL   0x00   // ADDR          Device Address-
#define CHANNR_VAL   0x00   // CHANNR        Channel Number-
#define FSCTRL1_VAL   0x06   // FSCTRL1       Frequency Synthesizer Control-
#define FSCTRL0_VAL   0x00   // FSCTRL0       Frequency Synthesizer Control-
#define FREQ2_VAL  0x0F   // FREQ2  0x10        Frequency Control Word  High Byte
#define FREQ1_VAL 0x80      // FREQ1  0xAF       Frequency Control Word  Middle Byte
#define FREQ0_VAL 0x00    // FREQ0  0x78       Frequency Control Word  Low Byte
#define MDMCFG4_VAL 0xCE //0x1E-500k   //0x1A-50k     // MDMCFG4 0x86      Modem Configuration- DATA RATE
#define  MDMCFG3_VAL 0x3B //0x3B-500k //0xF8-50k    // MDMCFG3 0x83       Modem Configuration- DATA RATE
#define MDMCFG2_VAL  0x30   // MDMCFG2       Modem Configuration-
#define MDMCFG1_VAL   0x42   // MDMCFG1       Modem Configuration-
#define MDMCFG0_VAL  0xF8   // MDMCFG0       Modem Configuration-
#define DEVIATN_VAL   0x00   // DEVIATN //0x20 - 6.4khz, 0x54 -75kHz       Modem Deviation Setting-
#define MCSM2_VAL   0x07   // MCSM2         Main Radio Control State Machine Configuration
#define MCSM1_VAL   0x30   // MCSM1         Main Radio Control State Machine Configuration- CCA
#define MCSM0_VAL   0x18   // MCSM0         Main Radio Control State Machine Configuration-
#define  FOCCFG_VAL  0x16   // FOCCFG        Frequency Offset Compensation Configuration-
#define  BSCFG_VAL  0x6C   // BSCFG         Bit Synchronization Configuration-
#define AGCCTRL2_VAL   0x43   // AGCCTRL2      AGC Control-
#define  AGCCTRL1_VAL  0x40   // AGCCTRL1      AGC Control-
#define AGCCTRL0_VAL   0x91   // AGCCTRL0      AGC Control-
#define WOREVT1_VAL   0x87   // WOREVT1       High Byte Event0 Timeout
#define  WOREVT0_VAL  0x6B   // WOREVT0       Low Byte Event0 Timeout
#define WORCTRL_VAL   0xF8  // WORCTRL       Wake On Radio Control
#define  FREND1_VAL  0x56   // FREND1        Front End RX Configuration-
#define  FREND0_VAL  0x11  // FREND0        Front End TX Configuration-
#define  FSCAL3_VAL  0xE9   // FSCAL3        Frequency Synthesizer Calibration-
#define  FSCAL2_VAL  0x2A   // FSCAL2        Frequency Synthesizer Calibration-
#define  FSCAL1_VAL  0x00   // FSCAL1        Frequency Synthesizer Calibration-
#define FSCAL0_VAL   0x1F   // FSCAL0        Frequency Synthesizer Calibration-
#define  RCCTRL1_VAL  0x41   // RCCTRL1       RC Oscillator Configuration
#define RCCTRL0_VAL   0x00   // RCCTRL0       RC Oscillator Configuration
#define FSTEST_VAL   0x59   // FSTEST        Frequency Synthesizer Calibration Control
#define PTEST_VAL   0x7F   // PTEST         Production Test
#define  AGCTEST_VAL  0x3F   // AGCTEST       AGC Test
#define TEST2_VAL   0x81   // TEST2         Various Test Settings-
#define TEST1_VAL   0x35   // TEST1         Various Test Settings-
#define  TEST0_VAL  0x0B   // TEST0 0X09        Various Test Settings-

RECEIVER REGISTER SETTINGS:

#define IOCFG2_VAL 0x2E  // IOCFG2        GDO2 Output Pin Configuration-
#define IOCFG1_VAL 0x2E  // IOCFG1        GDO1 Output Pin Configuration
#define IOCFG0_VAL 0x0D  // IOCFG0        GDO0 Output Pin Configuration-
#define FIFOTHR_VAL 0x47   // FIFOTHR       RX FIFO and TX FIFO Thresholds
#define SYNC1_VAL   0xD3   // SYNC1         Sync Word  High Byte
#define SYNC0_VAL    0x91   // SYNC0         Sync Word  Low Byte
#define PKTLEN_VAL   0xFF   // PKTLEN        Packet Length-
#define PKTCTRL1_VAL   0x00   // PKTCTRL1   0x04   Packet Automation Control-
#define PKTCTRL0_VAL   0x32   // PKTCTRL0   0x05 for variable pkt mode  Packet Automation Control-
#define ADDR_VAL   0x00   // ADDR          Device Address-
#define CHANNR_VAL   0x00   // CHANNR        Channel Number-
#define FSCTRL1_VAL   0x06   // FSCTRL1       Frequency Synthesizer Control-
#define FSCTRL0_VAL   0x00   // FSCTRL0       Frequency Synthesizer Control-
#define FREQ2_VAL  0x0F   // FREQ2  0x10        Frequency Control Word  High Byte
#define FREQ1_VAL 0x80      // FREQ1  0xAF       Frequency Control Word  Middle Byte
#define FREQ0_VAL 0x00    // FREQ0  0x78       Frequency Control Word  Low Byte
#define MDMCFG4_VAL 0xCE //0x1E-500k   //0x1A-50k     // MDMCFG4 0x86      Modem Configuration- DATA RATE
#define  MDMCFG3_VAL 0x3B //0x3B-500k //0xF8-50k    // MDMCFG3 0x83       Modem Configuration- DATA RATE
#define MDMCFG2_VAL  0x30   // MDMCFG2       Modem Configuration-
#define MDMCFG1_VAL   0x42   // MDMCFG1       Modem Configuration-
#define MDMCFG0_VAL  0xF8   // MDMCFG0       Modem Configuration-
#define DEVIATN_VAL   0x00   // DEVIATN //0x20 - 6.4khz, 0x54 -75kHz       Modem Deviation Setting-
#define MCSM2_VAL   0x07   // MCSM2         Main Radio Control State Machine Configuration
#define MCSM1_VAL   0x30   // MCSM1         Main Radio Control State Machine Configuration- CCA
#define MCSM0_VAL   0x18   // MCSM0         Main Radio Control State Machine Configuration-
#define  FOCCFG_VAL  0x16   // FOCCFG        Frequency Offset Compensation Configuration-
#define  BSCFG_VAL  0x6C   // BSCFG         Bit Synchronization Configuration-
#define AGCCTRL2_VAL   0x43   // AGCCTRL2      AGC Control-
#define  AGCCTRL1_VAL  0x40   // AGCCTRL1      AGC Control-
#define AGCCTRL0_VAL   0x91   // AGCCTRL0      AGC Control-
#define WOREVT1_VAL   0x87   // WOREVT1       High Byte Event0 Timeout
#define  WOREVT0_VAL  0x6B   // WOREVT0       Low Byte Event0 Timeout
#define WORCTRL_VAL   0xF8  // WORCTRL       Wake On Radio Control
#define  FREND1_VAL  0x56   // FREND1        Front End RX Configuration-
#define  FREND0_VAL  0x11  // FREND0        Front End TX Configuration-
#define  FSCAL3_VAL  0xE9   // FSCAL3        Frequency Synthesizer Calibration-
#define  FSCAL2_VAL  0x2A   // FSCAL2        Frequency Synthesizer Calibration-
#define  FSCAL1_VAL  0x00   // FSCAL1        Frequency Synthesizer Calibration-
#define FSCAL0_VAL   0x1F   // FSCAL0        Frequency Synthesizer Calibration-
#define  RCCTRL1_VAL  0x41   // RCCTRL1       RC Oscillator Configuration
#define RCCTRL0_VAL   0x00   // RCCTRL0       RC Oscillator Configuration
#define FSTEST_VAL   0x59   // FSTEST        Frequency Synthesizer Calibration Control
#define PTEST_VAL   0x7F   // PTEST         Production Test
#define  AGCTEST_VAL  0x3F   // AGCTEST       AGC Test
#define TEST2_VAL   0x81   // TEST2         Various Test Settings-
#define TEST1_VAL   0x35   // TEST1         Various Test Settings-
#define  TEST0_VAL  0x0B   // TEST0 0X09        Various Test Settings-

Please let me know if further information is required.

Thanks,

Vignesh

0 Sverre over 9 years ago in reply to vignesh M S

TI__Mastermind 39860 points

OOK only works up to 250 kbps. Please refer to the data sheet. In your settings you have used 500 kbps.

Furthermore, the RX filter BW needs to be wide enough to capture the transmitted signal bandwidth.

As mentioned in previous post, to find the optimum register settings for OOK operation please refer to design note DN022; www.ti.com/lit/SWRA215E

0 vignesh M S over 9 years ago in reply to Sverre

Expert 1180 points

Hi Sveere,

Thank you very much for your information. I followed tge design note DN022 and now, I'm able to demodulate the logic '1' levels at the receiver perfectly. But for logic '0' levels, it is totally distorted and shows a sequence of random high-low transitions. I even tested the receiver by directly connecting the SMA port of RX with a function generator and varied the power levels at the fixed center frequency. I had programmed the TX power levels to be -40 and -60 dBm for bit 1 and bit 0 respectively and the decision boundary was set such that the power level of bit '0' must be at least 16 dB lower than the bit '1'. In this case, the receiver demodulates the ASK signals with power levels up to around -70 dBm as logic 1 and for power levels below -70 dBm, the demodulated signal is completely distorted. Please find the register settings below.

PS: It would be of great help if you can explain the tradeoff's involved in RX Bandwidth, sensitivity, and data rate. For my settings, I have provided a maximum RX BW of 812 KHz and data rate of 20 kbps.

Center Frequency: 400.1 MHz

Modulation Format: ASK

Data rate: 20 kbps

TX power: bit '1': -40 dBm, bit '0': -60 dBm

Transmitter Settings:

#define IOCFG2_VAL 0x2E  // IOCFG2        GDO2 Output Pin Configuration-
#define IOCFG1_VAL 0x2E  // IOCFG1        GDO1 Output Pin Configuration
#define IOCFG0_VAL 0x2D  // IOCFG0        GDO0 Output Pin Configuration-
#define FIFOTHR_VAL 0x07   // FIFOTHR       RX FIFO and TX FIFO Thresholds
#define SYNC1_VAL   0xD3   // SYNC1         Sync Word  High Byte
#define SYNC0_VAL    0x91   // SYNC0         Sync Word  Low Byte
#define PKTLEN_VAL   0xFF   // PKTLEN        Packet Length-
#define PKTCTRL1_VAL   0x00  // PKTCTRL1   0x04   Packet Automation Control-
#define PKTCTRL0_VAL   0x32   // PKTCTRL0   0x05 for variable pkt mode  Packet Automation Control-
#define ADDR_VAL   0x00   // ADDR          Device Address-
#define CHANNR_VAL   0x00   // CHANNR        Channel Number-
#define FSCTRL1_VAL   0x0E   // FSCTRL1       Frequency Synthesizer Control-
#define FSCTRL0_VAL   0x00   // FSCTRL0       Frequency Synthesizer Control-
#define FREQ2_VAL  0x0F   // FREQ2  0x10        Frequency Control Word  High Byte
#define FREQ1_VAL 0x63      // FREQ1  0xAF       Frequency Control Word  Middle Byte
#define FREQ0_VAL 0x72    // FREQ0  0x78       Frequency Control Word  Low Byte
#define MDMCFG4_VAL 0x09 //0x1E-500k   //0x1A-50k     // MDMCFG4 0x86      Modem Configuration- DATA RATE
#define  MDMCFG3_VAL 0x93 //0x3B-500k //0xF8-50k    // MDMCFG3 0x83       Modem Configuration- DATA RATE
#define MDMCFG2_VAL  0x33   // MDMCFG2       Modem Configuration-
#define MDMCFG1_VAL   0x42   // MDMCFG1       Modem Configuration-
#define MDMCFG0_VAL  0xF8   // MDMCFG0       Modem Configuration-
#define DEVIATN_VAL   0x00   // DEVIATN //0x20 - 6.4khz, 0x54 -75kHz       Modem Deviation Setting-
#define MCSM2_VAL   0x07   // MCSM2         Main Radio Control State Machine Configuration
#define MCSM1_VAL   0x30   // MCSM1         Main Radio Control State Machine Configuration- CCA
#define MCSM0_VAL   0x18   // MCSM0         Main Radio Control State Machine Configuration-
#define  FOCCFG_VAL  0x1D   // FOCCFG        Frequency Offset Compensation Configuration-
#define  BSCFG_VAL  0x1C   // BSCFG         Bit Synchronization Configuration-
#define AGCCTRL2_VAL   0x04   // AGCCTRL2      AGC Control-
#define  AGCCTRL1_VAL  0x00   // AGCCTRL1      AGC Control-
#define AGCCTRL0_VAL   0x92   // AGCCTRL0      AGC Control-
#define WOREVT1_VAL   0x87   // WOREVT1       High Byte Event0 Timeout
#define  WOREVT0_VAL  0x6B   // WOREVT0       Low Byte Event0 Timeout
#define WORCTRL_VAL   0xF8  // WORCTRL       Wake On Radio Control
#define  FREND1_VAL  0xB6   // FREND1        Front End RX Configuration-
#define  FREND0_VAL  0x11  // FREND0        Front End TX Configuration-
#define  FSCAL3_VAL  0xE9   // FSCAL3        Frequency Synthesizer Calibration-
#define  FSCAL2_VAL  0x2A   // FSCAL2        Frequency Synthesizer Calibration-
#define  FSCAL1_VAL  0x00   // FSCAL1        Frequency Synthesizer Calibration-
#define FSCAL0_VAL   0x1F   // FSCAL0        Frequency Synthesizer Calibration-
#define  RCCTRL1_VAL  0x41   // RCCTRL1       RC Oscillator Configuration
#define RCCTRL0_VAL   0x00   // RCCTRL0       RC Oscillator Configuration
#define FSTEST_VAL   0x59   // FSTEST        Frequency Synthesizer Calibration Control
#define PTEST_VAL   0x7F   // PTEST         Production Test
#define  AGCTEST_VAL  0x3F   // AGCTEST       AGC Test
#define TEST2_VAL   0x88   // TEST2         Various Test Settings-
#define TEST1_VAL   0x31   // TEST1         Various Test Settings-
#define  TEST0_VAL  0x0B   // TEST0 0X09        Various Test Settings-

Receiver Settings:

#define IOCFG2_VAL 0x2E  // IOCFG2        GDO2 Output Pin Configuration-
#define IOCFG1_VAL 0x2E  // IOCFG1        GDO1 Output Pin Configuration
#define IOCFG0_VAL 0x0D  // IOCFG0        GDO0 Output Pin Configuration-
#define FIFOTHR_VAL 0x07   // FIFOTHR       RX FIFO and TX FIFO Thresholds
#define SYNC1_VAL   0xD3   // SYNC1         Sync Word  High Byte
#define SYNC0_VAL    0x91   // SYNC0         Sync Word  Low Byte
#define PKTLEN_VAL   0xFF   // PKTLEN        Packet Length-
#define PKTCTRL1_VAL   0x00  // PKTCTRL1   0x04   Packet Automation Control-
#define PKTCTRL0_VAL   0x32   // PKTCTRL0   0x05 for variable pkt mode  Packet Automation Control-
#define ADDR_VAL   0x00   // ADDR          Device Address-
#define CHANNR_VAL   0x00   // CHANNR        Channel Number-
#define FSCTRL1_VAL   0x0E   // FSCTRL1       Frequency Synthesizer Control-
#define FSCTRL0_VAL   0x00   // FSCTRL0       Frequency Synthesizer Control-
#define FREQ2_VAL  0x0F   // FREQ2  0x10        Frequency Control Word  High Byte
#define FREQ1_VAL 0x63      // FREQ1  0xAF       Frequency Control Word  Middle Byte
#define FREQ0_VAL 0x72    // FREQ0  0x78       Frequency Control Word  Low Byte
#define MDMCFG4_VAL 0x09 //0x1E-500k   //0x1A-50k     // MDMCFG4 0x86      Modem Configuration- DATA RATE
#define  MDMCFG3_VAL 0x93 //0x3B-500k //0xF8-50k    // MDMCFG3 0x83       Modem Configuration- DATA RATE
#define MDMCFG2_VAL  0x33   // MDMCFG2       Modem Configuration-
#define MDMCFG1_VAL   0x42   // MDMCFG1       Modem Configuration-
#define MDMCFG0_VAL  0xF8   // MDMCFG0       Modem Configuration-
#define DEVIATN_VAL   0x00   // DEVIATN //0x20 - 6.4khz, 0x54 -75kHz       Modem Deviation Setting-
#define MCSM2_VAL   0x07   // MCSM2         Main Radio Control State Machine Configuration
#define MCSM1_VAL   0x30   // MCSM1         Main Radio Control State Machine Configuration- CCA
#define MCSM0_VAL   0x18   // MCSM0         Main Radio Control State Machine Configuration-
#define  FOCCFG_VAL  0x1D   // FOCCFG        Frequency Offset Compensation Configuration-
#define  BSCFG_VAL  0x1C   // BSCFG         Bit Synchronization Configuration-
#define AGCCTRL2_VAL   0x04   // AGCCTRL2      AGC Control-
#define  AGCCTRL1_VAL  0x00   // AGCCTRL1      AGC Control-
#define AGCCTRL0_VAL   0x92   // AGCCTRL0      AGC Control-
#define WOREVT1_VAL   0x87   // WOREVT1       High Byte Event0 Timeout
#define  WOREVT0_VAL  0x6B   // WOREVT0       Low Byte Event0 Timeout
#define WORCTRL_VAL   0xF8  // WORCTRL       Wake On Radio Control
#define  FREND1_VAL  0xB6   // FREND1        Front End RX Configuration-
#define  FREND0_VAL  0x11  // FREND0        Front End TX Configuration-
#define  FSCAL3_VAL  0xE9   // FSCAL3        Frequency Synthesizer Calibration-
#define  FSCAL2_VAL  0x2A   // FSCAL2        Frequency Synthesizer Calibration-
#define  FSCAL1_VAL  0x00   // FSCAL1        Frequency Synthesizer Calibration-
#define FSCAL0_VAL   0x1F   // FSCAL0        Frequency Synthesizer Calibration-
#define  RCCTRL1_VAL  0x41   // RCCTRL1       RC Oscillator Configuration
#define RCCTRL0_VAL   0x00   // RCCTRL0       RC Oscillator Configuration
#define FSTEST_VAL   0x59   // FSTEST        Frequency Synthesizer Calibration Control
#define PTEST_VAL   0x7F   // PTEST         Production Test
#define  AGCTEST_VAL  0x3F   // AGCTEST       AGC Test
#define TEST2_VAL   0x88   // TEST2         Various Test Settings-
#define TEST1_VAL   0x31   // TEST1         Various Test Settings-
#define  TEST0_VAL  0x0B   // TEST0 0X09        Various Test Settings-

Thanks again,

Vignesh

0 Sverre over 9 years ago in reply to vignesh M S

TI__Mastermind 39860 points

Sensitivity vs RX BW: For the same data rate, the sensitivity drops by 3 dB for every doubling of RX BW. If you change the RX BW from BW1 to BW2 the sensitivity will change by 10log(BW1/BW2). Note that every 6 dB improvement in the link budget (e.g. sensitivity) gives a theoretical improvement in range of a factor 2.

Sensititivity vs data rate: For the same RX filter BW, the sensitivity drops (theoretically) by 3 dB for every doubling of data rate. Simplified, the energy pr bit will be cut in half with every doubling of data rate.

812 kHz RX BW is definitely on the high side for 20 kbps data rate. 100 kHz RX filter BW is sufficient, but note that the crystal accuracy also affects the required RX BW.

Looking at your settings I think you should try different values for AGCCTRL2. With 812 kHz RX BW AGCCTRL2.MAGN_TARGET = 4 seems a bit low. Try the following: AGCCTRL2,1,0 = 0xC7 00 B2

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Programming the transmitted power level in cc1101 in ASK/OOk mode