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the RF signal at the shoulder is too high

Derong Yuan
Intellectual 310 points
Other Parts Discussed in Thread: CC430F5137, TEST2, CC1101, CC1120

Hi,

I am developing a CC430F5137 based  RF product but I found the RF signals at the side of the spectrum chart is too high.

Please advise.

Thanks a million.

-derong

dyuan@seabreeze.ca

The picture below is the RF spectrum chart.

Below is the RF settings and part of the code.

//// Modulation = 2- GFSK

//carrier frequency = 868.3mHz 

//deviation =50khz
//receiver channel filter band width =464kHz
//xtal freq =26Mhz

//data rate =175kBaud

//optimized for sensitivity

RF_SETTINGS rfSettings = {
0x0c, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x21, // FREQ2 Frequency control word, high byte.
0x65, // FREQ1 Frequency control word, middle byte.
0x6A, // FREQ0 Frequency control word, low byte.
0x3c, // MDMCFG4 Modem configuration.
0xb9, // MDMCFG3 Modem configuration.
0x13, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x50, // DEVIATN Modem deviation setting (when FSK modulation enabled).
0x56, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end TX configuration.
0x30, // MCSM1 Main Radio Control State Machine configuration 1.
0x00, // MCSM0 Main Radio Control State Machine configuration.
0x1D, // FOCCFG Frequency Offset Compensation Configuration.
0x1C, // BSCFG Bit synchronization Configuration.
0xC7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xB0, // AGCCTRL0 AGC control.
0xEA, // FSCAL3 Frequency synthesizer calibration.
0x2A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x1F, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x81, // TEST2 Various test settings.
0x35, // TEST1 Various test settings.
0x09, // TEST0 Various test settings.
// 0x47, // FIFOTHR RXFIFO and TXFIFO thresholds.
0x40, // FIFOTHR RXFIFO and TXFIFO thresholds.
0x29, // IOCFG2 GDO2 output pin configuration.
0x06, // IOCFG0 GDO0 output pin configuration. Refer to SmartRF?Studio
// User Manual for detailed pseudo register explanation.
0x04, // PKTCTRL1 Packet automation control.
0x04, // PKTCTRL0 Packet automation control.
0x00, // ADDR Device address.
0x05 // PKTLEN Packet length.
};

main()

{

// Initialize I/O ports and set up port mapping 

.......

//------------------------------------------------------------------------------
//reset the PATABLE value
PATABLE_VAL = 0x50; // 0XC4-- 10 dBm;
// 0X50-- 0 dBm;
// 0X2D-- -6 dBm;
// 0X26-- -12dBm;
// 0x05-- -30dBm;
// 0xc0-- max
//ResetRadioCore
// Strobes SRES -> sets radio in SLEEP mode
Strobe(RF_SRES);// Reset the Radio Core
Strobe(RF_SNOP);// Reset Radio Pointer

//InitRadio
// Set the High-Power Mode Request Enable bit so LPM3 can be entered
// with active radio enabled
PMMCTL0_H = 0xA5;
PMMCTL0_L |= PMMHPMRE_L;
PMMCTL0_H = 0x00;

WriteRfSettings(&rfSettings);
WriteSinglePATable(PATABLE_VAL);
// Set up SYNC WORD
WriteSingleReg(SYNC1, SYNC_WORD_MSB);
WriteSingleReg(SYNC0, SYNC_WORD_LSB);
//change FIFO_THR back to 0x40
WriteSingleReg(PKTCTRL1, (rfSettings.fifothr & 0xF0));

state = STATE_SLEEP;
//------------------------------------------------------------------------------
/* MCU clock system (UCS) initialization
* - Start the 32768Hz crystal oscillator XT1
* - Configure the FLL to generate 8MHz clock using XT as reference
* - MCLK = SMCLK = 244 * fXT1 = 7.995392MHz from DCO/2.
*/
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 = SELA_2+SELS_3+SELM_3; //ACLK = REFO, MCLK=SMCLK=DCOCLK.
UCSCTL6 = XT2OFF & msk_1 | //XT2 is off
XT1OFF & msk_1; // XT1 is Off

__bis_SR_register(SCG0); // disable FLL pulling of DCO
UCSCTL0 = 0x0000; // set DCO to lowest tap
// FLL loop divide-by-2, Fsys/Fxt1 ratio = 243+1 = 244
UCSCTL2 = FLLD__2 | 243;
UCSCTL1 = DCORSEL_5; // good for 10..20MHz, we run Fdco = 16MHz and divide
// by 2 to make sure that clock duty cycle = 50% since
// we run at the 8MHz max limit for PMMCOREV = 0.
__bic_SR_register(SCG0); // re-enable FLL control
// maximum FLL settling delay = 1024 * f_MCLK / f_FLLREF
__delay_cycles(250000lu);

bTimeout = 100; // try max 100ms
// wait for ALL oscillator fault flags to become clear
while (SFRIFG1 & OFIFG)
{
__delay_cycles (8000lu); // delay ~1ms
// clear individual flags
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
SFRIFG1 &= ~OFIFG; // clear sum flag
  if (--bTimeout == 0)
  {
  //something wrong
  SOFTWARE_BOR_REBOOT
  }
}
UCSCTL4 = SELA__XT1CLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV;

//Initialize timers/counters

.......

//Initialize some variables

......

// the following code is used to transmit RF signals only

while(1)
{
CLRWDT_16s

TxBuffer[2] = miniFriend_1;
TxBuffer[3] = miniFriend_2;
TxBuffer[4] = miniFriend_3;
TxBuffer[5] = RF_BUTTON;

RF_Transmit(20); //issue alarm 10s
}

// the function below is to be called by the main() function above

void RF_Transmit(unsigned char time)
{
unsigned char i;

CLRWDT_16s
PATABLE_VAL = 0xc4; // 0XC4-- 10 dBm;
// 0X50-- 0 dBm;
// 0X2D-- -6 dBm;
// 0X26-- -12dBm;
// 0x05-- -30dBm;
// 0xc0-- max

WriteSinglePATable(PATABLE_VAL);

g_qHalfSecTick =time;
while(g_qHalfSecTick)
{
for(i=1;i<3;i++)
{
CLRWDT_16s

TxBuffer[0] = TxBuffer[i*2];
TxBuffer[1] = TxBuffer[i*2+1];

Strobe(RF_SIDLE);
Strobe(RF_SFRX);
Strobe(RF_SFTX);
Strobe(RF_SCAL);

while ((Strobe(RF_SNOP) & 0xF0) != 0x00 );

state = STATE_TX;

// Set up 2 preamble bytes
WriteSingleReg(MDMCFG1, (rfSettings.mdmcfg1 & 0x8f));
// Set up 16 bit sync word (16/16)
WriteSingleReg(MDMCFG2, (rfSettings.mdmcfg2 & 0xf4) | 0x02);

// Disable CRC at end of packet
WriteSingleReg(PKTCTRL0, (rfSettings.pktctrl0 & ~0x04));
//disable appending RSSI and LQI info at the payload
WriteSingleReg(PKTCTRL1, (rfSettings.pktctrl1 & ~0x04));
// Stay in TX (send preamble) after finishing packet transmission
WriteSingleReg(MCSM1 , (rfSettings.mcsm1 & 0xfc) | 0x02);

RF1AIES |= BIT9;
RF1AIFG &= ~BIT9; // Clear pending interrupts
RF1AIE |= BIT9; // Enable TX end-of-packet interrupt
// The packet length is the complete TxBuffer
TxBufferLength = 2;
// Set up packet length
WriteSingleReg(PKTLEN, 2);
WriteBurstReg(RF_TXFIFOWR, TxBuffer, TxBufferLength);
Strobe( RF_STX );

T_LEARN =3; //1.5s
while(T_LEARN >0)
{
if (state != STATE_TX)
{
break;
}
}
}
}

PATABLE_VAL = 0x50; // 0XC4-- 10 dBm;
// 0X50-- 0 dBm;
// 0X2D-- -6 dBm;
// 0X26-- -12dBm;
// 0x05-- -30dBm;
// 0xc0-- max

WriteSinglePATable(PATABLE_VAL);
}

  • 0
    TI__Mastermind 39860 points
    Your plot seems reasonable. You will pass ETSI EN300 220 V2.4.1 modulation bandwidth requirements so I do not understand your question.

    Regarding register settings. Use "175 kbaud, +/-95 kHz deviation" as starting point and change the deviation to 50 kHz. This ensures that some of the registers related to receiver bandwidth are set correctly (e.g FIFOTHR, AGCCTRLx, TEST2/1, FREND1)
  • 0 in reply to Sverre
    Intellectual 310 points

    Thank you for the comments Sverre. But my product has just failed in the emission level test of the ETSI EN300 220 V2.4.1. So I was asked to make the transmitting power (dB) down below the limit of -25DB for the bandwidth 868.0Mhz to 868.7Mhz by any means. Please advise.

    Below is the description of the emission level copy/paste from the ETSI EN300 220 V2.4.1:

  • 0 in reply to Derong Yuan
    TI__Mastermind 39860 points
    In your original plot you used a RBW of 50 kHz. You shall use 1 kHz, 10 kHz or 100 kHz depending on the offset from the 868.0 and 868.6 MHz band edges. When you do the measurements you should be in continuous TX, transmitting random data. Do not send packets as the there will be splattering effects when switching the PA on and off.

    The measurement should be done in 4 steps and the limits are
    1) -30 dBm at frequencies below 868.0 MHz and above 868.6 MHz. RBW = 1 kHz
    2) -36 dBm at frequencies below 867.8 MHz and above 868.8 MHz. RBW = 1 kHz
    3) -36 dBm at frequencies below 867.6 MHz and above 869.0 MHz. RBW = 10 kHz
    4) -36 dBm at frequencies below 867.0 MHz and above 869.6 MHz. RBW = 100 kHz
  • 0 in reply to Sverre
    Intellectual 310 points

    here is the RF setting generated from SmartRF for continuous Tx and transmitting random data:

    RF_SETTINGS rfSettings = {
    0x0c, // FSCTRL1 Frequency synthesizer control.
    0x00, // FSCTRL0 Frequency synthesizer control.
    0x21, // FREQ2 Frequency control word, high byte.
    0x65, // FREQ1 Frequency control word, middle byte.
    0x6A, // FREQ0 Frequency control word, low byte.
    0x3c, // MDMCFG4 Modem configuration.
    0xb9, // MDMCFG3 Modem configuration.
    0x10, // MDMCFG2 Modem configuration.
    0x22, // MDMCFG1 Modem configuration.
    0xF8, // MDMCFG0 Modem configuration.
    0x00, // CHANNR Channel number.
    0x50, // DEVIATN Modem deviation setting (when FSK modulation enabled).
    0xb6, // FREND1 Front end RX configuration.
    0x10, // FREND0 Front end TX configuration.
    0x30, // MCSM1 Main Radio Control State Machine configuration 1.
    0x10, // MCSM0 Main Radio Control State Machine configuration.
    0x1D, // FOCCFG Frequency Offset Compensation Configuration.
    0x1C, // BSCFG Bit synchronization Configuration.
    0xC7, // AGCCTRL2 AGC control.
    0x00, // AGCCTRL1 AGC control.
    0xB0, // AGCCTRL0 AGC control.
    0xEA, // FSCAL3 Frequency synthesizer calibration.
    0x2A, // FSCAL2 Frequency synthesizer calibration.
    0x00, // FSCAL1 Frequency synthesizer calibration.
    0x1F, // FSCAL0 Frequency synthesizer calibration.
    0x59, // FSTEST Frequency synthesizer calibration.
    0x81, // TEST2 Various test settings.
    0x35, // TEST1 Various test settings.
    0x09, // TEST0 Various test settings.
    // 0x47, // FIFOTHR RXFIFO and TXFIFO thresholds.
    0x40, // FIFOTHR RXFIFO and TXFIFO thresholds.
    0x0b, // IOCFG2 GDO2 output pin configuration.
    0x2d, // IOCFG0 GDO0 output pin configuration. Refer to SmartRF?Studio
    // User Manual for detailed pseudo register explanation.
    0x04, // PKTCTRL1 Packet automation control.
    0x22, // PKTCTRL0 Packet automation control.
    0x00, // ADDR Device address.
    0x05 // PKTLEN Packet length.
    };

    below is the testing software:

    //reset the PATABLE value
    PATABLE_VAL = 0x50; // 0XC4-- 10 dBm;
    // 0X50-- 0 dBm;
    // 0X2D-- -6 dBm;
    // 0X26-- -12dBm;
    // 0x05-- -30dBm;
    // 0xc0-- max
    //ResetRadioCore
    // Strobes SRES -> sets radio in SLEEP mode
    Strobe(RF_SRES);// Reset the Radio Core
    Strobe(RF_SNOP);// Reset Radio Pointer

    //InitRadio
    // Set the High-Power Mode Request Enable bit so LPM3 can be entered
    // with active radio enabled
    PMMCTL0_H = 0xA5;
    PMMCTL0_L |= PMMHPMRE_L;
    PMMCTL0_H = 0x00;

    WriteRfSettings(&rfSettings);
    WriteSinglePATable(PATABLE_VAL);
    // Set up SYNC WORD
    WriteSingleReg(SYNC1, SYNC_WORD_MSB);
    WriteSingleReg(SYNC0, SYNC_WORD_LSB);
    //change FIFO_THR back to 0x40
    WriteSingleReg(PKTCTRL1, (rfSettings.fifothr & 0xF0));

    state = STATE_SLEEP;
    //------------------------------------------------------------------------------
    /* MCU clock system (UCS) initialization
    * - Start the 32768Hz crystal oscillator XT1
    * - Configure the FLL to generate 8MHz clock using XT as reference
    * - MCLK = SMCLK = 244 * fXT1 = 7.995392MHz from DCO/2.
    */
    UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
    UCSCTL4 = SELA_2+SELS_3+SELM_3; //ACLK = REFO, MCLK=SMCLK=DCOCLK.
    UCSCTL6 = XT2OFF & msk_1 | //XT2 is off
    XT1OFF & msk_1; // XT1 is Off

    __bis_SR_register(SCG0); // disable FLL pulling of DCO
    UCSCTL0 = 0x0000; // set DCO to lowest tap
    // FLL loop divide-by-2, Fsys/Fxt1 ratio = 243+1 = 244
    UCSCTL2 = FLLD__2 | 243;
    UCSCTL1 = DCORSEL_5; // good for 10..20MHz, we run Fdco = 16MHz and divide
    // by 2 to make sure that clock duty cycle = 50% since
    // we run at the 8MHz max limit for PMMCOREV = 0.
    __bic_SR_register(SCG0); // re-enable FLL control
    // maximum FLL settling delay = 1024 * f_MCLK / f_FLLREF
    __delay_cycles(250000lu);

    bTimeout = 100; // try max 100ms
    // wait for ALL oscillator fault flags to become clear
    while (SFRIFG1 & OFIFG)
    {
    __delay_cycles (8000lu); // delay ~1ms
    // clear individual flags
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
    SFRIFG1 &= ~OFIFG; // clear sum flag
    if (--bTimeout == 0)
    {
    //something wrong
    SOFTWARE_BOR_REBOOT
    }
    }
    //ACLK = XT1 (default), SMCLK = DCOCLKDIV (default), MCLK = DCOCLKDIV (default)
    UCSCTL4 = SELA__XT1CLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV;
    // UCSCTL5 = 0; reset default = 0, all clock output dividers = 1:1
    // UCSCTL8 = 0x77; reset default = 0x77, see UG!
    //------------------------------------------------------------------------------
    // Start TA0 in continous mode with 8192Hz clock derived from ACLK/XT1
    // no overtime interrup
    TA0CCTL0 = 0; // initially disable all TA0 CC interrupts
    TA0CCTL1 = 0;
    TA0CCTL2 = 0;
    TA0CCTL3 = 0;
    TA0CCTL4 = 0;


    Strobe( RF_SIDLE );
    Strobe( RF_STX );

    while(1)
    {
    CLRWDT_16s
    }

    but the measured RF signals at the shoulder are still high.

  • 0 in reply to Derong Yuan
    Intellectual 310 points

    I download the "slac525.zip" and unzip it.  Then load the example code as a workspace "RF_Examples_IAR.eww" into IAR Embedded Workbench IDE.

    Compile the code "Asynchronous_comm_Tx.c" in project "Asynchronous_comm-Tx_MHZ_868", then run the compiled code  in EM_CC430F5137-900 evaluation board.

    Below is the plot for conducted emission measured the with a USB mini spectrum analyzer from Triarchy Tech. 

    Hard to say it can pass the CE test.

    Please advise.

    Thanks.

     

  • 0 in reply to Derong Yuan
    TI__Mastermind 39860 points
    Please see my post dated October 18 on how to do the measurements. The spectrum analyzer needs to be set according to the standard.
  • 0 in reply to Sverre
    Intellectual 310 points

    Thank you very Sverre.

    My spectrum analyzer (model: TSA4G1, S/N: CN41800329)  is a USB driven RF equipment from Triarchy. The RBW selection is auto/50Khz/100Khz/200Khz/500Khz. So I choose the auto for the RBW of 1Khz or 10kHz.

    the software code is tested in a TI's EM-CC430F5137-900 eval board.

    the RF power shown in the plots below are conducted test result. 

    the picture below shows the spectrum analyser and the eval board.

    the  RF setting in SmartRF is:

    the RF register settings are:

    #define uint8 unsigned char


    //RF1A.h
    typedef struct S_RF_SETTINGS

    {
    uint8 iocfg2; // GDO2 Output Configuration
    uint8 iocfg0; // GDO0 Output Configuration
    uint8 fifothr; // RX FIFO and TX FIFO Thresholds
    uint8 pktctrl0; // Packet Automation Control
    uint8 fsctrl1; // Frequency Synthesizer Control
    uint8 freq2; // Frequency Control Word, High Byte
    uint8 freq1; // Frequency Control Word, Middle Byte
    uint8 freq0; // Frequency Control Word, Low Byte
    uint8 mdmcfg4; // Modem Configuration
    uint8 mdmcfg3; // Modem Configuration
    uint8 mdmcfg2; // Modem Configuration
    uint8 deviatn; // Modem Deviation Setting
    uint8 mcsm0; // Main Radio Control State Machine Configuration
    uint8 foccfg; // Frequency Offset Compensation Configuration
    uint8 worctrl; // Wake On Radio Control
    uint8 fscal3; // Frequency Synthesizer Calibration
    uint8 fscal2; // Frequency Synthesizer Calibration
    uint8 fscal1; // Frequency Synthesizer Calibration
    uint8 fscal0; // Frequency Synthesizer Calibration
    uint8 test2; // Various Test Settings
    uint8 test1; // Various Test Settings
    uint8 test0; // Various Test Settings
    } RF_SETTINGS;


    // Rf settings for CC430
    RF_SETTINGS rfSettings =

    {
    0x0B, // IOCFG2 GDO2 Output Configuration
    0x2D, // IOCFG0 GDO0 Output Configuration
    0x47, // FIFOTHR RX FIFO and TX FIFO Thresholds
    0x22, // PKTCTRL0 Packet Automation Control
    0x06, // FSCTRL1 Frequency Synthesizer Control
    0x21, // FREQ2 Frequency Control Word, High Byte
    0x66, // FREQ1 Frequency Control Word, Middle Byte
    0x66, // FREQ0 Frequency Control Word, Low Byte
    0x3C, // MDMCFG4 Modem Configuration
    0xB9, // MDMCFG3 Modem Configuration
    0x10, // MDMCFG2 Modem Configuration
    0x50, // DEVIATN Modem Deviation Setting
    0x10, // MCSM0 Main Radio Control State Machine Configuration
    0x16, // FOCCFG Frequency Offset Compensation Configuration
    0xFB, // WORCTRL Wake On Radio Control
    0xEA, // FSCAL3 Frequency Synthesizer Calibration
    0x2A, // FSCAL2 Frequency Synthesizer Calibration
    0x00, // FSCAL1 Frequency Synthesizer Calibration
    0x1F, // FSCAL0 Frequency Synthesizer Calibration
    0x81, // TEST2 Various Test Settings
    0x35, // TEST1 Various Test Settings
    0x09, // TEST0 Various Test Settings
    };

    below are 3 measurements for the conducted RF test:

    1. to measure the central RF power the spectrum analyser setting is:

    the RF plot is:

     2. to measure the RF power before 868.0Mhz the spectrum analyser setting is:

    the RF plot is:

    3.  to measure the RF power after 868.7Mhz  the spectrum analyser setting is:

    the RF plot is:

    Below RF plot is what I found from TER's reponse to a post by Konstantin  in TI's forum " CC1101 compliance with EN300-220-1":

    I don't know how TER could get the near perfect RF spectrum plot.

    But he did not answer Konstantin's question: if CC430F5137 can be used in his alarm product which has passed the EN300-220-1 standard with cc1120. 

  • 0 in reply to Derong Yuan
    TI__Mastermind 39860 points

    Your spectrum analyzer cannot be used to measure the modulation bandwidth (MBW) according to EN 300 220. When you select RBW = "auto" the BW will not be 1 kHz or 10 kHz.

    Below are plots showing MBW for the different RBW and limits. Data rate is 175 kbps, deviation +/-50 kHz, GFSK modulation, 868.3 MHz.

    RBW = 1 kHz. Limit: -30 dBm. F1 and F2 are 868.0 MHz and 868.6 MHz (band edge) 

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/156/1kHz-RBW-BandEdge.WMF 

    RBW = 1 kHz. Limit: -36 dBm. F1 and F2 are 867.8 MHz and 868.8 MHz (band edge +/- 200 kHz) 

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/156/1kHz-RBW-BandEdge-plus-200kHz.WMF

    RBW = 10 kHz. Limit: -36 dBm. F1 and F2 are 867.6 MHz and 869.0 MHz (band edge +/- 400 kHz) 

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/156/10kHz-RBW-BandEdge-plus-400kHz.WMF

    RBW = 100 kHz. Limit: -36 dBm. F1 and F2 are 867.0 MHz and 869.6 MHz (band edge +/- 1000 kHz) 

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/156/100kHz-RBW-BandEdge-plus-1000kHz.WMF

  • 0 in reply to Sverre
    Intellectual 310 points

    Thank you very much for your quick response Sverre.

    I tested the code again in the eval board EM-CC430F5137-900 and measured the RF power with the same spectrum analyser with RBW =100kHz. Then I compared my plot with your plot (measured with RWB=100kHz) and found they look too much different.

    Could you post your RF settings generated from SmartRF so I can see if my RF settings are wrong? Do you test your software in the eval board EM-CC430F5137-900?

    my spectrum plot with RBW =100khz:

    your spectrum plot with RBW=100khz you posted at Nov1, 2016 7:31AM:

  • 0 in reply to Derong Yuan
    TI__Mastermind 39860 points
    Sorry for the delayed response. I used CC430EM for my testing. The register settings are those you get from SmartRF Studio if you select "175 kBaud, Dev 95 kHz" and simply change the deviation to +/-50 kHz
  • 0 in reply to Derong Yuan
    Prodigy 10 points

    The Triarchy TSA5G35 spectrum analyzer can have very poor sideband spurs, poor phase noise, and modulation from internal digital noise, which will affect the results. It's fine for troubleshooting and detecting signals, but it's not a suitable instrument for compliance testing.