CC430F5137: what mean is "MSP430: Warning: CPU is currently OFF and debugging capabilities will be limited."?

Hello,

When you see this warning, are you still able to run the code from the debugger window? Are you running the program on a custom board or a TI board?

Are any of your clock sources from an external oscillator? Can you check the oscillator fault flags in UCSCTL7?

Thanks,
Ryan

Your question 1> When you see this warning, are you still able to run the code from the debugger window?

=> I try to press "F5" and "F6" buttons, I found below message in Console.

     "MSP430: Warning: CPU is currently OFF and debugging capabilities will be limited."

Your question 2> Are you running the program on a custom board or a TI board? 

=> custom board.

Your question 3> Are any of your clock sources from an external oscillator?

=> maybe, my clock source from 26Mhz external oscillator. but, i'm not sure. (sorry, I'm not HW engineer)

Your question 4> Can you check the oscillator fault flags in UCSCTL7? 

=> This register value is zero. (value of XT2OFFG, XT1HFOFFG, XT1LFOFFG and DCOFFG are zero.)

below is screen shot of critical situation.

You can find "MSP430: Warning: CPU is currently OFF and debugging capabilities will be limited." in Console window.

Hello,

Do you have more custom boards you can load the program on to see if they have the same behavior? Are you using 4-wire JTAG or Spy-Bi-Wire to debug the boards? Can you ensure that the passive components - especially the  resistor and capacitor on the RST line - on the debugging signal lines for your custom board match the figures in the MSP430 Hardware Tools User's Guide (Figure 2-1 for 4-wire JTAG or Figure 2-2 for Spy-Bi-Wire)? If you are using an MSP-FET to program the board, the signal lines between the MSP-FET and the board IC should not exceed 20 centimeters.

You may also want to check your CCS project properties to ensure the watchdog timer is held during cinit. In the CCS window, go to Project >> Properties >> Build >> MSP430 Linker >> Basic Options, and make sure that the box next to "Hold watchdog timer during cinit auto-initializtion (--cinit_hold_wdt)" says "on".

Thanks,

Ryan

1) I'm using MSP-FET. maybe signal lines is over 20 centimeter. photo about connection is below

2) I can't find "Hold watchdog timer during cinit auto-initializtion (--cinit_hold_wdt)". Where is it?

3) As you think, My issue is Hardware or CCS side. right?

That is the page where you should be able to find the hold watchdog timer setting. Are you using the most updated version of CCS? If not, what version of CCS are you using?

The signal lines do look like they are longer than 20 centimeters because it includes the length of the black ribbon cable and the second ribbon cable, so they should be shortened if possible. You can also try slowing down the Debug connection speed. In your project in the "targetConfigs" folder, open the active .ccxml file. Go to the "Advanced" tab, click on "MSP430" and change "JTAG/SBW Speed" to "Slow" and save the file.

Regards,

Ryan

my CCS version is below.

Hello,

Were you able to test with a different board, shorten the communication lines, or slow down the JTAG/SBW speed? Have any of these helped?

Thanks,
Ryan