CC1200: Status byte reserved bits

Its custom board and I'am using MSP432.. I'am not sending preamble and sync because I'am sending smart preamble ..

It's odd to me what triggers this bug but I now can replicate it whenever I want.. So when I'am sending message and there is condition to send another wright after current message is sent this bug happens. But when I send message, first I go ti IDLE, then to SNIFF, then to IDLE and at last to TX.

Seeing in that document you point to me, and knowing that those bits say how many bytes I can write to TX FIFO now I suspect that for some reason at the initialization of transmit when I send 128 bytes to TXFIFO to fill it up it stays empty and therefore I newer receive interrupt (for threshold) that will refill TX FIFO or end transmit. I assume that is empty because after burst write of 128 bytes and after sending STX I get that 0x0F (15 or more bytes left to wright to TX FIFO) and when it works that status byte is 0x00 so TX FIFO is full.

I don't see what is different when I send message and send two in row expect that i'am crossing from TX ->IDLE->SNIFF->IDLE->TX relatively faster then usual where c1220 is longer in SNIFF and then I go to TX. But before TX initialization I go to IDLE,  send SFTX and SFRX and then I set all registers accordingly, execute SCAL and then fill TX FIFO and send STX.

/*Disabling sync word  */
	CC1200_SingleWrite(CC1200_ADDRESS_SYNC_CFG1 ,0x00);
    /*Disabling preamble  */
    CC1200_SingleWrite(CC1200_ADDRESS_PREAMBLE_CFG1 ,0x00);
    /* Asserts the GPIO0 when the TX FIFO has underflowed */
    CC1200_SingleWrite(CC1200_ADDRESS_IOCFG0, 0x05);
    /* Asserts the GPIO2 when the TX FIFO is emptied below the threshold */
    CC1200_SingleWrite(CC1200_ADDRESS_IOCFG2, 0x02);
    /* Configure infinite packet mode */
    CC1200_SingleWrite(CC1200_ADDRESS_PKT_CFG0, 0x40);
    /* Disabling CRC, append status and whitening */
    CC1200_SingleWrite(CC1200_ADDRESS_PKT_CFG1, 0x00);

    /* Set FIFO threshold to assert when the TX FIFO falls below 127 - TX_FIFO_THR bytes */
    CC1200_SingleWrite(CC1200_ADDRESS_FIFO_CFG, TX_FIFO_THR);

    CC1200_SendCommand(SCAL);
	while(CC1200_GetStatus() != CC1200_STATUS_IDLE);

    /* Fill the TX FIFO whole even if the packet is smaller */
    CC1200_BurstWrite(tranBuffer, CC1200_ADDRESS_FIFO, FIFO_SIZE);

    /* Check how many bytes will be left after the first interrupt */
    if(packetLength <= AVAILABLE_TXFIFO_BYTES)
    {
        cc1200_bytesLeft = 0;
    }
    else
    {
        cc1200_bufferOffset = tranBuffer + FIFO_SIZE;
        cc1200_bytesLeft    = packetLength - AVAILABLE_TXFIFO_BYTES;

        CC1200_PrepareDMA(cc1200_bufferOffset, AVAILABLE_TXFIFO_BYTES, cc1200_state);
    }

    /* Enable and configure interrupt */
    MAP_GPIO_interruptEdgeSelect(CC1200_GPIO_PORT, CC1200_GPIO0, GPIO_LOW_TO_HIGH_TRANSITION);
    MAP_GPIO_interruptEdgeSelect(CC1200_GPIO_PORT, CC1200_GPIO2, GPIO_HIGH_TO_LOW_TRANSITION);
    MAP_GPIO_clearInterruptFlag(CC1200_GPIO_PORT, CC1200_GPIO0 | CC1200_GPIO2);
    MAP_GPIO_enableInterrupt(CC1200_GPIO_PORT, CC1200_GPIO0 | CC1200_GPIO2);

    /* Start transfer */
    status = CC1200_SendCommand(STX);

    return status;

EDIT: Also after this bug, I can go to SNIFF again and next time sending is ok ... So it's really problem with that writing to TX FIFO where I apperently don't write anything to TX FIFO and therefore newer exit transmit (and I'am talking here about my state in MCU for RF module .. don't really know in what state CC1200 is at that point).. I have never had this kind of bug so watching what is different after recent coding for smart preamble. Beside some different register configuration, I have direct burst read of RX FIFO when I receive CRC OK for time stamp packet:

CC1200_BurstRead(timeStampBuffer, CC1200_ADDRESS_FIFO, 2);
timeStamp = timeStampBuffer[1];

where CC1200_BurstRead is: 

	CC1200_SelectModule();

	/* Command byte that says burst read from starting address */
	CC1200_TransmitByte(startingAddress | CC1200_READ_BURST);
	statusByte	= CC1200_ReceiveByte();

	for(i = 0; i<length; i++)
	{
		CC1200_TransmitByte(SNOP);
		outputBuffer[i] = CC1200_ReceiveByte();
	}

	CC1200_DeselectModule();

 Can this cause something do go wrong with TX FIFO.. Also before I used automatic Calibration  with SETTLING register and now I manually calibrate with SCAL and at one point of receiving I have SWORST. That are differences on before and now where before I have never seen this bug. 

But again, no problem when sending message until I have condition to send next message while sending current message, so don't see what can cause this. Even if there is data racing somewhere because I use some shared variables when forming message, I don't see how that cause this because filling TX FIFO is done whatever pointer points to. So my best guess is that I have to wait some time when in SNIFF before sending command SIDLE but I doubt it?

EDIT2: After placing some delay of 2ms before sending SIDLE command it didn't have that bug. Also tried with 1ms and there it was again. So with 2ms delay I don't have that problem but I now have 2ms more regarding response time. Can you try sending CC1200 to SNIFF and then fast to TX to repeat this behavior. Don't know exactly how fast transition is because there is some code (cycles ) to be executed on 48MHz before sending SIDLE directly after going to SNIFF (SWOR).

No its not shown.. It's before that register changes.

CC1200_SendCommand(SIDLE);
    while(CC1200_GetStatus() != CC1200_STATUS_IDLE);
    CC1200_SendCommand(SFRX);
    CC1200_SendCommand(SFTX);

I doubt that I'am in wrong state. You can see that I wait until I'am in IDLE after SIDLE. Also its not shown that on every CS pull down I wait until SO pulls down when chip is ready. Another thing is that I'am taking into account for FIFO errors when in TX/RX - underflow/overflow with interrupts so if that happens I flush corresponding FIFO buffer.

This problem is only happening like I said in that case when next message is send wright after other is sent, rather when I go to SNIFF and wright after that to IDLE->TX.  At least I think so :D 

If you think that there is no problem regarding how much time passed after sending SWOR and setting CS and pulling CS low and sending SIDLE  then I'll try to find some other possible cause to my problem. At this point waiting 2ms before sending SIDLE (it may be less because I haven't try some time between 1 and 2 ms) eliminates my problem.

EDIT:  I changed a little bit wait and instead of waiting before sending SIDLE 2ms, i putted timer that starts after initializing SNIFF and in TX initialization before SIDLE I check if timer is still running and if it is I wait to pass. If timer configured <=1ms problem occurs, if  >1 & <1.3ms it returns that status byte 0x0F but it appears that in this case it put some bytes above TX_THR so TX can be terminated because it either underflowed at some point or it successfully transmit message (not sure at this point but my MCU exits its TX state and initializes SNIFF again) and for  timer configured >=1.3ms there is no problem. I really don't now why this is but maybe you guys can figure it out, or maybe its some big coincidence and problem is somewhere in my software :D. I will post it if I find it :D  

Regards.