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BOOSTXL-CC1125: PKT_SYNC_RXTX interrupt

Harikrishnan R S
Expert 1670 points
Part Number: BOOSTXL-CC1125
Other Parts Discussed in Thread: CC1125

Hi,

Does the PKT_SYNC_RXTX interrupt checks for a valid CRC ? I am currently using the PKT_SYNC_RXTX as my interrupt mechanism and have set the PKT_CFG1 _ CRC_CFG  as 0x01.

  • 0
    TI__Guru**** 317180 points
    From the UserGuide: RX: Asserted when sync word has been received and de-asserted at the
    end of the packet. Will de-assert when the optional address and/or
    length check fails or the RX FIFO overflows/underflows.

    See the examples here: processors.wiki.ti.com/.../Perf_value_line_easylink

    => The MCU has to check if a valid packet is received etc
  • 0 in reply to TER
    Expert 1670 points

    Thank You TER,

    Thanks for the reply.

    But my doubt is regarding the process that CC1125 do when there is a CRC mismatch. 

  • 0 in reply to Harikrishnan R S
    TI__Guru**** 317180 points
    That is up to the MCU, see the examples I linked to. Typically you want to flush the FIFO.
  • 0 in reply to TER
    TI__Guru* 86131 points
    If you want a signal that only gives you an interrupt when a packet is received with CRC OKm you can use the CRC_OK sugnal (IOCFGx = 0x07). In that case yu should set CRC_AUTOFLUSH = 1. to avoid an overflow of the RX FIFO and you would probably want to set TERM_ON_BAD_PACKET_EN = 0.
    Siri
  • 0 in reply to Siri
    Expert 1670 points

    Thank You Siri,

    Thanks for the reply.

    So, the only possibility to use CRC in PKT_SYNC_RXTX is by doing it manually in the controller part, right ?

  • 0 in reply to Harikrishnan R S
    TI__Guru* 86131 points

    No, that is not correct. You can use CRC even if you are using PKT_SYNC_RXTX. The way the signal work is that you will get an interrupt (rising edge) when a sync word is received and a falling edge when a packet is received or when filtering/overflow happens. If you have enabled CRC and CRC_AUTOFLUSH, the packet will be left in the FIFO if CRC is OK and automatically flushed from the FIFO if the CRC Fails. That means that when you get an interrupt on falling edge of the PKT_SYNC_RXTX signal you do not know if there is anything in the FIFO or not. You can check NUM_RXBYTE, and if the FIFO is not empty you know that the packet in there has CRC OK. If you enable CRC but have CRC_AUTOFLUSH disabled, the packet will be put in the FIFO regardless of the CRC beeing OK or not (assuming you do not use other kinds of filtering). You then need to check if the CRC is OK by reading the status byte in the end of the packet (if appended) or by reading the PKT_CRC_OK bit in the LQI_VAL register.

    Siri

  • 0 in reply to Siri
    Expert 1670 points

    Thank You Siri,

    Thanks for the reply.

    That helped me out in resolving my issue.