Our network must operate from -40 to +60C. We use EasyLink-v2.30.00 with TI-RTOS as testing application. Software was load into 2 modules based on CC1350 (see attached picture for silicon revision). Data are transferred via UART.
Central frequency - 869 MHz.
Bitrate - 50 KHz.
Deviation - 25 KHz.
Receiver bandwith - 100 KHz.
Then both modules were placed in freezer with -30C. After that carrier frequency on the first module gets shift 200 KHz, and on the second 300 KHz, and data transfer stopped.
After issuing hardware reset on the first module - carrier returns to its nominal 869 MHz. Data transfer is not recovers.
Hardware reset on the second module - carrier returns to its nominal 869 MHz and data transfer is fully recovers at -30C!!!
Question: what we must do to get network with required operating temperatures?
Our settings:
ccfg.c
#define CCFG_FORCE_VDDR_HH 0x1 // Force VDDR voltage to the factory HH setting (FCFG1..VDDR_TRIM_HH)
#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0 // Alternative DC/DC setting enabled
#define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0xC // Special VMIN level (2.5V) when forced VDDR HH voltage
#define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x1 // Enable
#define SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 0x0 // 31mA
#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1 // Disable override
#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT 0x0 // Delta = 0
#define SET_CCFG_MODE_CONF_1_XOSC_MAX_START 0x10 // 1600us
#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF // Signed delta value +1 to apply to the VDDR_TRIM_SLEEP target (0xF=-1=default=no compensation)
#define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x0 // Use the DC/DC during recharge in powerdown
#define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x0 // Use the DC/DC during active mode
#define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // Special setting to enable forced VDDR HH voltage
#define SET_CCFG_MODE_CONF_VDDR_CAP 0x3A // Unsigned 8-bit integer representing the min. decoupling capacitance on VDDR in units of 100nF
#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1 // Temperature compensation on VDDR sleep trim disabled (default)
#define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x2 // LF XOSC
#define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x1 // Don't apply cap-array delta
#define SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF // Signed 8-bit value, directly modifying trimmed XOSC cap-array value
#define SET_CCFG_EXT_LF_CLK_DIO 0x01 // DIO number if using external LF clock
#define SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 0x800000 // RTC increment representing the external LF clock frequency
#define SET_CCFG_MODE_CONF_XOSC_FREQ 0x3 // HF source is a 24 MHz xtal (default)
Nikolay A. Neudobnov. Systems, modules and components. Moscow, Russia.
