CC1125: GPIO and SPI Status during Reset

Register information for the IOCFG registers, including reset values, see page 71 in www.ti.com/.../swru295e.pdf

Hi TER,

That is the information for the pins after the reset has occurred. What behavior is expected while the device is held in reset, i.e. when RESET_N is held low?

Regards,
Akash

The reset value is also valid when the reset is active (held low) since the reset is async.

Hi TER,

For example, can you help me understand what will be the expected behavior on GPIO3 while the chip is held in reset? It says the default output selection will be PKT_SYNC_RXTX, but this does not tell me what to expect on the pin.

Regards,
Akash

I would assume '0' but it needs some digging to find out (or a measurement) . But before I start, what is the background for the question?

Hi TER,

We have 2 CC1125 devices (for use in different bands) in our design, one is always active while the other is in reset. As this is the case, for simplicity, we would like to have some of the pins tied together.

Can you please confirm what the expected behavior will be for the GPIO and SO lines?

Thank you,
Akash

Hi TER,

Thank you for confirming, that seems to be aligned with the behavior we are seeing on our end.

Regards,
Akash