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RTOS/CC1350: Available memory ranges: FLASH

Wade Zhang
Intellectual 725 points
Part Number: CC1350

Tool/software: TI-RTOS

Hello All，

"/Applications/ti/simplelink_cc13x0_sdk_1_60_00_21/source/ti/blestack/common/cc26xx/ccs/cc26xx_app.cmd", line 124: error #10099-D: program will not fit into available memory. placement with alignment fails for section ".cinit" size 0x57e . Available memory ranges:
FLASH size: 0xf000 unused: 0x50e max hole: 0x508
FLASH_LAST_PAGE size: 0x1000 unused: 0x244 max hole: 0x244
error #10010: errors encountered during linking; "simple_peripheral_cc1350lp_app_FlashROM.out" not built

Can the size of this mapping address be changed?

  • 0
    TI__Guru 56590 points
    Hello Wade,
    Does the example fail out-of-the-box (OoB)?
  • 0
    TI__Guru 56590 points
    I believe you can move it. Have you disabled code optimizations? Perhaps increasing optimization will make it all fit, if not you will likely have to modify your linker command file to get it all to fit. How to do this? See:
    processors.wiki.ti.com/.../Linker_Command_File_Primer

    .cinit is the actual value for initialized ram variables and stored in flash ( the values, not the ram variables ). You probably added code which increased the size of several of the code sections (maybe not just .cinit), preventing it fitting in the available spaces.
    processors.wiki.ti.com/.../Build_Errors_in_CCS

    .cinit is described here:
    processors.wiki.ti.com/.../C28x_Compiler_-_Understanding_Linking