Part Number: CC1312R
Hi,
I have a question from customer about CC1312 Bootloader Backdoor.
Suppose Bootloader Backdoor is enabled and BL_LELEL is active low, what is the minimum timing the pin used for level checking(backdoor pin) needs to be settled at low level?
Please see the timing ‘t’ in below figure. Customer wants this value, t(min).
I knew TRM description says the pin needs to be low upon reset, so an expectation is the pin is low at RESET_N rising edge.
But in fact the pin level is checked by software(startup ROM code), so there is some delay from RESET_N release timing.
According to CC1312 datasheet, there is timing specification “Reset to Active” in Table 5-2.
http://www.ti.com/lit/ds/symlink/cc1312r.pdf
Q1) I thinks the “750 to 2500 us” corresponds to the timing between “RESET_N rising edge” to “ROM code starts running”. Correct?
Q2) If so, the backdoor pin sampling will be done after 750usec at least. So the backdoor pin needs to be settled at low level by this point, correct?
Q3) What is DC characteristics(VIH) for RESET_N ? Same as GPIO (0.8*VDDS) ?
Above information will help customer minimize system cost.
Thanks and reagrds,
KoT
