CC1201: Unexpected zero data

I have taken the cc120x_easy_link example and modified it to use the 500 kbps settings from Studio and fixed packet length.

Below are my register settings and the  modified RX and TX functions:

static const registerSetting_t preferredSettings[]=
{
  {CC120X_IOCFG2,            0x06},
  {CC120X_SYNC_CFG1,         0xA8},
  {CC120X_DEVIATION_M,       0x47},
  {CC120X_MODCFG_DEV_E,      0x2F},
  {CC120X_DCFILT_CFG,        0x1E},
  {CC120X_PREAMBLE_CFG0,     0x8A},
  {CC120X_IQIC,              0x00},
  {CC120X_CHAN_BW,           0x01},
  {CC120X_MDMCFG1,           0x42},
  {CC120X_MDMCFG0,           0x05},
  {CC120X_SYMBOL_RATE2,      0xC9},
  {CC120X_SYMBOL_RATE1,      0x99},
  {CC120X_SYMBOL_RATE0,      0x99},
  {CC120X_AGC_REF,           0x2F},
  {CC120X_AGC_CS_THR,        0xF8},
  {CC120X_AGC_CFG2,          0x60},
  {CC120X_AGC_CFG1,          0x12},
  {CC120X_AGC_CFG0,          0x84},
  {CC120X_FIFO_CFG,          0x00},
  {CC120X_FS_CFG,            0x12},
  {CC120X_PKT_CFG2,          0x00},
  {CC120X_PKT_CFG0,          0x00},
  {CC120X_PKT_LEN,           0xFF},
  {CC120X_FREQOFF_CFG,       0x23},
  {CC120X_MDMCFG2,           0x00},
  {CC120X_FREQ2,             0x56},
  {CC120X_FREQ1,             0xCC},
  {CC120X_FREQ0,             0xCC},
  {CC120X_IF_ADC1,           0xEE},
  {CC120X_IF_ADC0,           0x10},
  {CC120X_FS_DIG1,           0x04},
  {CC120X_FS_DIG0,           0xA3},
  {CC120X_FS_CAL1,           0x40},
  {CC120X_FS_CAL0,           0x0E},
  {CC120X_FS_DIVTWO,         0x03},
  {CC120X_FS_DSM0,           0x33},
  {CC120X_FS_DVC1,           0xF7},
  {CC120X_FS_DVC0,           0x0F},
  {CC120X_FS_PFD,            0x00},
  {CC120X_FS_PRE,            0x6E},
  {CC120X_FS_REG_DIV_CML,    0x1C},
  {CC120X_FS_SPARE,          0xAC},
  {CC120X_FS_VCO0,           0xB5},
  {CC120X_IFAMP,             0x0D},
  {CC120X_XOSC5,             0x0E},
  {CC120X_XOSC1,             0x03},
};

static void runTX(void)
{
    // Initialize packet buffer of size PKTLEN
    uint8 txBuffer[PKTLEN] = {0};
    
    // Set the fixed packet length to PKTLEN
    uint8 writeByte = PKTLEN;
    cc120xSpiWriteReg(CC120X_PKT_LEN, &writeByte, 1);

    // Connect ISR function to GPIO2
    ioPinIntRegister(IO_PIN_PORT_1, GPIO2, &radioTxISR);

    // Interrupt on falling edge
    ioPinIntTypeSet(IO_PIN_PORT_1, GPIO2, IO_PIN_FALLING_EDGE);

    // Clear ISR flag
    ioPinIntClear(IO_PIN_PORT_1, GPIO2);

    // Enable interrupt
    ioPinIntEnable(IO_PIN_PORT_1, GPIO2);

    // Update LCD
    updateLcd();

    // Infinite loop
    while(TRUE)
    {
        // Wait for button push
        if(bspKeyPushed(BSP_KEY_ALL))
        {
            // Continiously sent packets until button is pressed
            do
            {
                txBuffer[0] = packetCounter++;
                for (uint8 i = 1; i < PKTLEN; i++)
                {
                    txBuffer[i] = i;
                }
           
                // Write packet to TX FIFO
                cc120xSpiWriteTxFifo(txBuffer, sizeof(txBuffer));

                // Strobe TX to send packet
                trxSpiCmdStrobe(CC120X_STX);

                // Wait for interrupt that packet has been sent.
                // (Assumes the GPIO connected to the radioRxTxISR function is
                // set to GPIOx_CFG = 0x06)
                while(packetSemaphore != ISR_ACTION_REQUIRED);

                // Clear semaphore flag
                packetSemaphore = ISR_IDLE;

                // Update LCD
                updateLcd();
                
                // Wait for a random amount of time between each packet
                waitMs(3*(rand()%10+3));
                
            } while (!bspKeyPushed(BSP_KEY_ALL));
        }
    }
}


static void runRX(void) {

    uint8 rxBuffer[128] = {0};
    uint8 rxBytes;
    uint8 marcState;

    // Connect ISR function to GPIO2
    ioPinIntRegister(IO_PIN_PORT_1, GPIO2, &radioRxISR);

    // Interrupt on falling edge
    ioPinIntTypeSet(IO_PIN_PORT_1, GPIO2, IO_PIN_FALLING_EDGE);

    // Clear ISR flag
    ioPinIntClear(IO_PIN_PORT_1, GPIO2);

    // Enable interrupt
    ioPinIntEnable(IO_PIN_PORT_1, GPIO2);

    // Update LCD
    updateLcd();
    
    // Set the fixed packet length to PKTLEN
    uint8 writeByte = PKTLEN;
    cc120xSpiWriteReg(CC120X_PKT_LEN, &writeByte, 1);

    // Set radio in RX
    trxSpiCmdStrobe(CC120X_SRX);

    // Infinite loop
    while(TRUE) {

        // Wait for packet received interrupt
        if(packetSemaphore == ISR_ACTION_REQUIRED) {

            // Read number of bytes in RX FIFO
            cc120xSpiReadReg(CC120X_NUM_RXBYTES, &rxBytes, 1);

            // Check that we have bytes in FIFO
            if(rxBytes != 0) {

                // Read MARCSTATE to check for RX FIFO error
                cc120xSpiReadReg(CC120X_MARCSTATE, &marcState, 1);

                // Mask out MARCSTATE bits and check if we have a RX FIFO error
                if((marcState & 0x1F) == RX_FIFO_ERROR) {

                    // Flush RX FIFO
                    trxSpiCmdStrobe(CC120X_SFRX);
                } else {

                    // Read n bytes from RX FIFO
                    cc120xSpiReadRxFifo(rxBuffer, rxBytes);

                    // Check CRC ok (CRC_OK: bit7 in second status byte)
                    // This assumes status bytes are appended in RX_FIFO
                    // (PKT_CFG1.APPEND_STATUS = 1)
                    // If CRC is disabled the CRC_OK field will read 1
                    if(rxBuffer[rxBytes - 1] & 0x80) {

                        // Update packet counter
                        packetCounter++;
                    }
                }
            }

            // Update LCD
            updateLcd();

            // Reset packet semaphore
            packetSemaphore = ISR_IDLE;

            // Set radio back in RX
            trxSpiCmdStrobe(CC120X_SRX);
        }
    }
}

BR

Siri