Tool/software: TI-RTOS
The CC1310 TR document says that the SPI clock is SSIn_CLK = PERDMACLK / [CPSDVSR × (1 + SCR)]
CPSDVSR >= 2 so there is a maximum of 24MHz which is achieved for master mode with SCR == 0.
For slave mode, there is a note that the speed should be divided at least by 12 in total, so a maximum of 4MHz. In other words,SCR >= 3.
The TI-RTOS ssi.c driver has the following code:
void
SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk,
uint32_t ui32Protocol, uint32_t ui32Mode,
uint32_t ui32BitRate, uint32_t ui32DataWidth)
{
...
ASSERT(((ui32Mode == SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 2))) ||
((ui32Mode != SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 12))));
...
// Set the clock predivider.
ui32MaxBitRate = ui32SSIClk / ui32BitRate;
ui32PreDiv = 0;
do
{
ui32PreDiv += 2;
ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1;
}
while(ui32SCR > 255);
HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv;
// Set protocol and clock rate.
ui32SPH_SPO = (ui32Protocol & 3) << 6;
ui32Protocol &= SSI_CR0_FRF_M;
ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | (ui32DataWidth - 1);
HWREG(ui32Base + SSI_O_CR0) = ui32RegVal;
}
There is an assert for the 12 ratio but after that, nothing seems to be specific to slave mode. In other words, it seems possible to have SCR=0 in slave mode.
I'm confused why there is such note for slave mode. What is the real reason? As SPI is bi-directional, I can receive at 24MHz in master mode so there is nothing down the logic that would prevent from handling a SPI input at 24MHz. Is this limitation real or is it to be safe regarging the SPI FIFO?
