cc1200 rssi and agc in transparent mode

First some basics to understand your setup:

We have not tested performance in detail with transparent mode since our test systems are based on using the FIFO. 

I see from your register settings that you have set a sync word and PQT gating etc which are not available in transparent mode. Could you give some background for this? 

Why do you need to use transparent mode in this case? 

Thanks, TER:

    The sync word and pqt gating are left over from previous revision that used the cc1200 standard encoding in sniff mode.

In order to receive some of our legacy units I had to go to transparent mode and use our existing software that uses

Structure of Manchester encoding.

     Should I remove the pqt gating?

John

Ter:

   Yesterday there was a glitch in the posting software for a new question.

    I posted this twice because if I put CC1200 at the top then the forum selection below now gives

only one option and that Is low power mcu controllers.  So I left out the part number so it would 

allow me to select wireless sub Ghz.

John

Ter:

     I may have an inappropriate setting for the agc that is causing the RSSI to not update properly.

Also when the channel is changed it sometimes takes a long time to start receiving transmissions.  

This could indicate the agc isn't updating properly.

John

I don't think you have to remove the unused code but it will help if someone has to read the code in the future. Then the code should reflect the functions you are using and only those.

You could start  by looking into the AGC_REF value. The recommended setting for this RX BW is 0x2F, see the register description.

Are you able to do a "RSSI vs input level" measurement? Use a signal generator and apply a sine wave, read RSSI and the content of the AGC_GAIN3 register and increase in 1 dB steps. Then it's fairly easy to see how the AGC behave and based on that it's easier to cover what to change. 

Ter:

I changed the AGC_REF to 2F and used a  signal generator to run

an "RSSI vs input level" measurement.

     The RSSI reading is within 1db of the generator

Output (where i tested it) from -80 to -117dbm but it only reads rssi correctly the first time after reset.

So if I set the gen to -100dbm and read rssi it comes out -100.

If I then change the gen setting up or down the rssi reading stays -100. It is stuck.

I can read another rssi after resetting the system.

So the rssi reading is not updating.

John

Finally found it, TER:

   There is a default setting, AGC_CFG3, which I wasn't writing to that defaults to agc and rssi freeze!

this is the field AGC_SYNC_BEHAVIOUR.

Thanks,

John

Meaning that this one is solved? In that case: Good to hear!

thanks, Ter

John

Hi, Ter:

    Have the transparent serial receiver working well with agc and RSSI.  However it has some trouble starting up the receiver.

I can tell whether it is in rx mode using the nop command.  Often it drops out of receive and goes to idle.  May have to

setup the receiver several times initially to get it to stay in receive and not drop out to idle mode.  Once in receive it seems to 

stay there pretty well but we are watching for it to drop out of receive in testing.  The setup sequence is:

_disable_interrupts();

ResetCC1200(); //reset cc1200

WaitForIdleState(); //wait for idle state to be reached
registerConfig(); //12.5ms. configure radio in subs.c

// Calibrate radio:
WaitForIdleState(); //wait for idle state to be reached
trxSpiCmdStrobe(CC120X_SCAL); //in TranscInit.c 375us.

// Wait for calibration to be done (radio back in IDLE state)
WaitForIdleState(); //wait for idle state to be reached
//can now set freq since in idle mode:
FreqDes = Chan2Freq((unsigned int)Settings.RxChannel) ; // was uFixedXmtCh calc desired freq ??
SetFreq( FreqDes) ; //8=410-480, 24=136.7-160, 20=164-192 in subs.c

// Calibrate the RCOSC
calibrateRCOsc(); //calibrates rc osc then strobes chip into idle state

trxSpiCmdStrobe(CC120X_SWOR);        //SWOR takes to rec mode (ewor timer not set) TranscInit.c.
trxSpiCmdStrobe(CC120X_SRX);

SetTxRx(0); //set the ant switch to input for receiving
PAOn(0); //turn off PA just in case (setuprx)

_enable_interrupts();

} //end of SetupRx

 Hoping you have some ideas.

John Moore

From your code:

trxSpiCmdStrobe(CC120X_SWOR);        //SWOR takes to rec mode (ewor timer not set) TranscInit.c.
trxSpiCmdStrobe(CC120X_SRX);

This does not make sense since you should use either SWOR or SRX and the former is not valid for transparent mode. As showed in the state diagram, how you enter or exit RX is well defined. You should not have issues entering RX. 

Have you looked at the code examples on how to ensure that you are in IDLE before strobing RX? 

TER:

    Here is the wait for idle function:

void WaitForIdleState()

{

 static uint8 marcState, WITimeout;

    WITimeout=0;

    do {                //wait for radio to reach idle state (0x41)

           if(++WITimeout > 10)      //check for timeout

               return;

           cc120xSpiReadReg(CC120X_MARCSTATE, &marcState, 1);

       } while ((marcState & 0x1F) != 0x1);

}

I’m doing a calibrate RC osc after setting frequency as follows  (may not be needed):

void calibrateRCOsc(void)

{

    uint8 temp;

    // Read current register value

    cc120xSpiReadReg(CC120X_WOR_CFG0, &temp,1);

    // Mask register bit fields and write new values

    temp = (temp & 0xF9) | (0x02 << 1);

    // Write new register value

    cc120xSpiWriteReg(CC120X_WOR_CFG0, &temp,1);

    // Strobe IDLE to calibrate the RCOSC

    trxSpiCmdStrobe(CC120X_SIDLE);

    // Disable RC calibration

    temp = (temp & 0xF9) | (0x00 << 1);

    cc120xSpiWriteReg(CC120X_WOR_CFG0, &temp, 1);

}

TER:

    Looks like I need to give SRX to go to frequency synthesizer startup, then another SRX to 

go to receive mode??

Thanks,

John

TER:

    Looking at the flow chart on p6 of user guide.  It seems to show that once it is in idle mode, 

the command SWOR goes to Freq synthesizer startup, then SRX goes to receive mode.  This is 

what I've done.  It seems to work better than other approaches I've tried.  (but I may be doing something 

wrong.

John

TER:

   Here's the example that's available:

void main(void) {

// Initialize MCU and peripherals
initMCU();

// Write radio registers
registerConfig();

// Enter runRX, never coming back
runRX();
}

/*******************************************************************************
* @fn runRX
*
* @brief Puts radio in RX and waits for packets. Function assumes
* that status bytes are appended in the RX_FIFO
* Update packet counter and display for each packet received.
*
* @param none
*
* @return none
*/
static void runRX(void) {

uint8 rxBuffer[128] = {0};
uint8 rxBytes;
uint8 marcState;

// Connect ISR function to GPIO2
ioPinIntRegister(IO_PIN_PORT_1, GPIO2, &radioRxISR);

// Interrupt on falling edge
ioPinIntTypeSet(IO_PIN_PORT_1, GPIO2, IO_PIN_FALLING_EDGE);

// Clear ISR flag
ioPinIntClear(IO_PIN_PORT_1, GPIO2);

// Enable interrupt
ioPinIntEnable(IO_PIN_PORT_1, GPIO2);

// Update LCD
updateLcd();

// Set radio in RX
trxSpiCmdStrobe(CC120X_SRX);

// Infinite loop
while(TRUE) {

// Wait for packet received interrupt
if(packetSemaphore == ISR_ACTION_REQUIRED) {

// Read number of bytes in RX FIFO
cc120xSpiReadReg(CC120X_NUM_RXBYTES, &rxBytes, 1);

// Check that we have bytes in FIFO
if(rxBytes != 0) {

// Read MARCSTATE to check for RX FIFO error
cc120xSpiReadReg(CC120X_MARCSTATE, &marcState, 1);

// Mask out MARCSTATE bits and check if we have a RX FIFO error
if((marcState & 0x1F) == RX_FIFO_ERROR) {

// Flush RX FIFO
trxSpiCmdStrobe(CC120X_SFRX);
} else {

// Read n bytes from RX FIFO
cc120xSpiReadRxFifo(rxBuffer, rxBytes);

// Check CRC ok (CRC_OK: bit7 in second status byte)
// This assumes status bytes are appended in RX_FIFO
// (PKT_CFG1.APPEND_STATUS = 1)
// If CRC is disabled the CRC_OK field will read 1
if(rxBuffer[rxBytes - 1] & 0x80) {

// Update packet counter
packetCounter++;
}
}
}

// Update LCD
updateLcd();

// Reset packet semaphore
packetSemaphore = ISR_IDLE;

// Set radio back in RX
trxSpiCmdStrobe(CC120X_SRX);
}
}
}

/*******************************************************************************
* @fn radioRxISR
*
* @brief ISR for packet handling in RX. Sets packet semaphore
* and clears ISR flag
*
* @param none
*
* @return none
*/
static void radioRxISR(void) {

// Set packet semaphore
packetSemaphore = ISR_ACTION_REQUIRED;

// Clear ISR flag
ioPinIntClear(IO_PIN_PORT_1, GPIO2);
}

It doesn't do much except issue the SRX command.  Doesn't calibrate or turn on the

synthesizer.  Is this all that's needed?

I must be doing something wrong because I must set the frequency in order to get the 

receiver to start up.

John

"the command SWOR goes to Freq synthesizer startup, then SRX goes to receive mode.": No. Note that SWOR and SRX do the same in the state diagram, both go through the same stage from IDLE to RX:

If you see the setting on this register:

It depends how you have set fs_autocal if you have to do a SCAL or not. 

What exactly do you mean by "I must set the frequency in order to get the receiver to start up."

Thanks, TER:

    It has been such that setting the receive frequency after receiver setup has helped it startup.

I've been setting  SETTLING_CFG to 03 (every 4th time),  looks like it should be set to 01 (when going from idle to rx or tx).

John

TER:

    With settling_cfg set to 01 does this mean the config only needs one SRX command to go from

idle to rx?

John

You should always just issue one SRX command to go from IDLE to RX. 

TER:

   Have rec startup set to the following only and receiver doesn't start:

_disable_interrupts();

ResetCC1200(); //reset cc1200 rfsubs.c
WaitForIdleState(); //wait for idle state to be reached
registerConfig(); //12.5ms. configure radio in subs.c

WaitForIdleState(); //wait for idle state to be reached

//can now set freq since in idle mode:
FreqDes = Chan2Freq((unsigned int)Settings.RxChannel) ; // was uFixedXmtCh calc desired freq ??
SetFreq( FreqDes) ; //8=410-480, 24=136.7-160, 20=164-192 in subs.c

WaitForIdleState(); //wait for idle state to be reached

trxSpiCmdStrobe(CC120X_SRX);

RxCald=1; //indicates receiver was calibrated

SetTxRx(0); //set the ant switch to input for receiving
PAOn(0); //turn off PA just in case (setuprx)

_enable_interrupts();
} //end of SetupRx

TER:

    Here's the radio setup that works the best for us in transp serial mode right now.

SWOR starts up often the first time but usually takes more than one try.

Could be my other config settings for WOR are messing up the radio init??

John

ResetCC1200(); //reset cc1200 rfsubs.c
WaitForIdleState(); //wait for idle state to be reached
registerConfig(); //12.5ms. configure radio in subs.c

// Calibrate radio shouldn't need with autocal:

WaitForIdleState(); //wait for idle state to be reached
//can now set freq since in idle mode:
FreqDes = Chan2Freq((unsigned int)Settings.RxChannel) ; // was uFixedXmtCh calc desired freq ??
SetFreq( FreqDes) ; //8=410-480, 24=136.7-160, 20=164-192 in subs.c

WaitForIdleState(); //wait for idle state to be reached

trxSpiCmdStrobe(CC120X_SWOR);

//trxSpiCmdStrobe(CC120X_SRX);

//cc120xSpiReadReg(CC120X_MARCSTATE, &marcState, 1); //check the state. Doesn't rec with this
RxCald=1; //indicates receiver was calibrated

SetTxRx(0); //set the ant switch to input for receiving
PAOn(0); //turn off PA just in case (setuprx)

TER:

    Here's our current config file.  The same except has agc and RSSI unfrozen:

John

const registerSetting_t preferredSettings[]=
{
{CC120X_IOCFG3, 17}, //was 17=Carrier Sense. p3
{CC120X_IOCFG2, 16}, //16=carrier sense valid p4

//{CC120X_IOCFG3, 15}, //CCA. p3
//{CC120X_IOCFG2, 16}, //16=carrier sense valid p4

//{CC120X_IOCFG3, 49}, //read ext osc (625khz). Doesn't work
//{CC120X_IOCFG2, 0x04}, //cca
//{CC120X_IOCFG1, 0x00}, //make GPIO1 output & invert to high (see 3.4)
{CC120X_IOCFG0, 0x09}, //Ser rec PKT_SYNC_RXTX

{CC120X_SYNC3, 0x55}, //was AA, 55 7:0 sets MSB sync. AA for inverted
{CC120X_SYNC2, 0x55}, //was AA, 55, 7:0 sets MSB sync.
{CC120X_SYNC1, 0x55}, //was AA, 55, 05 7:0 sets MSB sync.
{CC120X_SYNC0, 0x56}, //was A9, 56 sets lsb of sync in 7:0. Orig A6
{CC120X_SYNC_CFG0, 0x88}, //**was 88. added PQT_EN=80 & PQT_Gating_En=0x08,b00= most strict. b10=strict_sync_check=3
{CC120X_SYNC_CFG1, 0x2C}, //**28=11 bits & 8 thresh. was 48. 4x=16bits, 8x=24bits, Ax=32 bits 7-5 len sync, 4:0=sync thresh
{CC120X_DEVIATION_M, 0x8D},
{CC120X_MODCFG_DEV_E, 0x08}, //08 for GFSK, 28 for 4GFSK GFSK/4FSK
{CC120X_DCFILT_CFG, 0x5D},
{CC120X_PREAMBLE_CFG1, 0x14}, //14=3bytes, 18=4b. 20=6b 10=2bytes e AA. was 24. 0x31=24bytes. 0x25=7bytes
{CC120X_PREAMBLE_CFG0, 0x8A}, //**was 8A PQT_EN=08
{CC120X_IQIC, 0xCB},
{CC120X_CHAN_BW, 0xAC}, //AC=9.46khz. AA=10khz
{CC120X_MDMCFG1, 0xA0}, //was E0. 80=carrier sense gate, 40=fifo en, Man mode=20, invert data=10
{CC120X_MDMCFG0, 0x45}, //transp mode
{CC120X_SYMBOL_RATE2, 0x4F}, //4f for normal 2400= 5f, 4800=6f or 9600 w/o manchester
{CC120X_SYMBOL_RATE1, 0x75},
{CC120X_SYMBOL_RATE0, 0x10},
{CC120X_AGC_REF, 0x2f}, //was 31
{CC120X_AGC_CS_THR, 0x8B}, //8B=-117, 8A=-118,88=-120, 8d=-115 was 8a, 92=-110dbm. 8F=-113, A6=-90dbm
{CC120X_AGC_CFG1, 0x42},
{CC120X_AGC_GAIN_ADJUST, 0x9c}, //9C=-100, 9D=-99. This is the RSSI offset valid when AGC_GAIN_ADJUST.GAIN_ADJUSTMENT = 0x00.
{CC120X_AGC_CFG0, 0x8c}, //8c=5 counts. Was 80=1 count for rssi
{CC120X_AGC_CFG3, 0x11}, //turns off agc freeze
{CC120X_FIFO_CFG, 0x00},
{CC120X_SETTLING_CFG, 0x01}, //do automatic autocal when going from idle to rx or tx
{CC120X_FS_CFG, 0x1B},
{CC120X_WOR_CFG0, 0x08}, //same
{CC120X_WOR_CFG1, 0x08}, //added
{CC120X_WOR_EVENT0_MSB, 0x01}, //0035=.6pre, 010A=1pre, 018f= 2pre, 0214=2.5pre, 029a=3pre
{CC120X_WOR_EVENT0_LSB, 0x8f}, //
{CC120X_PKT_CFG2, 0x03}, //0c=cca mode. CRc disabled, no status byte
{CC120X_PKT_CFG1, 0x00}, // 0x01=append RSSI. Adx check & crc disabled. This line needed to rec MCDT!
{CC120X_PKT_CFG0, 0x10}, //x18 pro 6bits, x10 EMIDS 4bits. fixed length=00 in bits 6:5, bit len in bits 4:2
//{CC120X_RFEND_CFG1, 0x30}, // x30 gives return to rx after rxing
{CC120X_RFEND_CFG0, 0x04}, //04:RX termination based on PQT. 0x1: Rx term based on CS. 0x30 gives return to rx after txing
{CC120X_PKT_LEN, 0x08}, //pktlen, packet length 02 +4 bits for emids, 6-3/4 for pro
{CC120X_IF_MIX_CFG, 0x1C},
{CC120X_FREQOFF_CFG, 0x23}, //FOC_EN=x20, FOC_KI_Factor=02 was 20
{CC120X_MDMCFG2, 0x0C},
{CC120X_TOC_CFG, 0xC0}, //** was 40 TOC limit 2%

{CC120X_SETTLING_CFG, 0x08}, //Cal FS going from idle to rec or tx

{CC120X_FREQ2, 0x5A},
{CC120X_FREQ1, 0x00},
{CC120X_FREQ0, 0x00},

{CC120X_IF_ADC1, 0xEE},
{CC120X_IF_ADC0, 0x10},
{CC120X_FS_DIG1, 0x07},
{CC120X_FS_DIG0, 0xAF},
{CC120X_FS_CAL1, 0x40},
{CC120X_FS_CAL0, 0x0E},
{CC120X_FS_DIVTWO, 0x03},
{CC120X_FS_DSM0, 0x33},
{CC120X_FS_DVC0, 0x17},
{CC120X_FS_PFD, 0x00},
{CC120X_FS_PRE, 0x6E},
{CC120X_FS_REG_DIV_CML, 0x1C},
{CC120X_FS_SPARE, 0xAC},
{CC120X_FS_VCO0, 0xB5},
//{CC120X_FS_CFG, 0x0B}, //136-160Mhz
{CC120X_XOSC5, 0x0E},
{CC120X_XOSC1, 0x03},
};

As written before, SWOR doesn't work with transparent. Use SRX

TER:

    The problem is that SRX doesn't work at all for me but SWOR works, albeit often slowly.

Could you try this on your test bench?

John

First what you have to do is clean up the code and remove everything that regards WOR since it's not relevant for transparent. Also remove register settings that have to do with packet handling. Transparent mode does not need anything special to work. Using the standard code example and setting the registers described in the UserGude should be sufficient.   

Then, it's not clear from what you describe what you actually see since, as written before, the radio should enter RX directly when strobing SRX. SWOR also start RX, but will also end RX. 

TER:

    I'm still using packet handling to transmit.

John

TER:

   I check for receive mode using the NOP command.  Returns IDLE if not REC.

John

TER:

     Should be able to clean out the packet stuff in config then put it back to setup tx.

John

TER:

    Removed all the WOR stuff from config file and changed mdmcfg1, agc_cfg1, agc_cfg0, and freqoff_cfg to 

the same as the example.  Now it won't start at all.  The rec setup is as follows:

ResetCC1200(); //reset cc1200 rfsubs.c
WaitForIdleState(); //wait for idle state to be reached
registerConfig(); //12.5ms. configure radio in subs.c

WaitForIdleState(); //wait for idle state to be reached

//can now set freq since in idle mode:
FreqDes = Chan2Freq((unsigned int)Settings.RxChannel) ; // was uFixedXmtCh calc desired freq ??
SetFreq( FreqDes) ; //8=410-480, 24=136.7-160, 20=164-192 in subs.c

WaitForIdleState(); //wait for idle state to be reached

trxSpiCmdStrobe(CC120X_SRX);

and the config file is:

const registerSetting_t preferredSettings[]=
{
{CC120X_IOCFG3, 17}, //was 17=Carrier Sense. p3
{CC120X_IOCFG2, 16}, //16=carrier sense valid p4

//{CC120X_IOCFG3, 15}, //CCA. p3
//{CC120X_IOCFG2, 16}, //16=carrier sense valid p4

//{CC120X_IOCFG3, 49}, //read ext osc (625khz). Doesn't work
//{CC120X_IOCFG2, 0x04}, //cca
//{CC120X_IOCFG1, 0x00}, //make GPIO1 output & invert to high (see 3.4)
{CC120X_IOCFG0, 0x09}, //Ser rec PKT_SYNC_RXTX

{CC120X_SYNC3, 0x55}, //was AA, 55 7:0 sets MSB sync. AA for inverted
{CC120X_SYNC2, 0x55}, //was AA, 55, 7:0 sets MSB sync.
{CC120X_SYNC1, 0x55}, //was AA, 55, 05 7:0 sets MSB sync.
{CC120X_SYNC0, 0x56}, //was A9, 56 sets lsb of sync in 7:0. Orig A6
{CC120X_SYNC_CFG0, 0x88}, //**was 88. added PQT_EN=80 & PQT_Gating_En=0x08,b00= most strict. b10=strict_sync_check=3
{CC120X_SYNC_CFG1, 0x2C}, //**28=11 bits & 8 thresh. was 48. 4x=16bits, 8x=24bits, Ax=32 bits 7-5 len sync, 4:0=sync thresh
{CC120X_DEVIATION_M, 0x8D},
{CC120X_MODCFG_DEV_E, 0x08}, //08 for GFSK, 28 for 4GFSK GFSK/4FSK
{CC120X_DCFILT_CFG, 0x5D},
{CC120X_PREAMBLE_CFG1, 0x14}, //14=3bytes, 18=4b. 20=6b 10=2bytes e AA. was 24. 0x31=24bytes. 0x25=7bytes
{CC120X_PREAMBLE_CFG0, 0x8A}, //**was 8A PQT_EN=08
{CC120X_IQIC, 0xCB},
{CC120X_CHAN_BW, 0xAC}, //AC=9.46khz. AA=10khz
{CC120X_MDMCFG1, 0x40}, //was E0. 80=carrier sense gate, 40=fifo en, Man mode=20, invert data=10
{CC120X_MDMCFG0, 0x45}, //transp mode
{CC120X_SYMBOL_RATE2, 0x4F}, //4f for normal 2400= 5f, 4800=6f or 9600 w/o manchester
{CC120X_SYMBOL_RATE1, 0x75},
{CC120X_SYMBOL_RATE0, 0x10},
{CC120X_AGC_REF, 0x2f}, //was 31
{CC120X_AGC_CS_THR, 0x8B}, //8B=-117, 8A=-118,88=-120, 8d=-115 was 8a, 92=-110dbm. 8F=-113, A6=-90dbm
{CC120X_AGC_CFG1, 0x51},
{CC120X_AGC_GAIN_ADJUST, 0x9c}, //9C=-100, 9D=-99. This is the RSSI offset valid when AGC_GAIN_ADJUST.GAIN_ADJUSTMENT = 0x00.
{CC120X_AGC_CFG0, 0xc7}, //8c=5 counts. Was 80=1 count for rssi
{CC120X_AGC_CFG3, 0x11}, //turns off agc freeze
{CC120X_FIFO_CFG, 0x00},
{CC120X_SETTLING_CFG, 0x01}, //do automatic autocal when going from idle to rx or tx
{CC120X_FS_CFG, 0x1B},
//{CC120X_WOR_CFG0, 0x08}, //same
//{CC120X_WOR_CFG1, 0x08}, //added
//{CC120X_WOR_EVENT0_MSB, 0x01}, //0035=.6pre, 010A=1pre, 018f= 2pre, 0214=2.5pre, 029a=3pre
//{CC120X_WOR_EVENT0_LSB, 0x8f}, //
{CC120X_PKT_CFG2, 0x03}, //0c=cca mode. CRc disabled, no status byte
{CC120X_PKT_CFG1, 0x00}, // 0x01=append RSSI. Adx check & crc disabled. This line needed to rec MCDT!
{CC120X_PKT_CFG0, 0x10}, //x18 pro 6bits, x10 EMIDS 4bits. fixed length=00 in bits 6:5, bit len in bits 4:2
//{CC120X_RFEND_CFG1, 0x30}, // x30 gives return to rx after rxing
{CC120X_RFEND_CFG0, 0x04}, //04:RX termination based on PQT. 0x1: Rx term based on CS. 0x30 gives return to rx after txing
{CC120X_PKT_LEN, 0x08}, //pktlen, packet length 02 +4 bits for emids, 6-3/4 for pro
{CC120X_IF_MIX_CFG, 0x1C},
{CC120X_FREQOFF_CFG, 0x22}, //FOC_EN=x20, FOC_KI_Factor=02 was 20
{CC120X_MDMCFG2, 0x0C},
{CC120X_TOC_CFG, 0xC0}, //** was 40 TOC limit 2%

{CC120X_SETTLING_CFG, 0x08}, //Cal FS going from idle to rec or tx

{CC120X_FREQ2, 0x5A},
{CC120X_FREQ1, 0x00},
{CC120X_FREQ0, 0x00},

{CC120X_IF_ADC1, 0xEE},
{CC120X_IF_ADC0, 0x10},
{CC120X_FS_DIG1, 0x07},
{CC120X_FS_DIG0, 0xAF},
{CC120X_FS_CAL1, 0x40},
{CC120X_FS_CAL0, 0x0E},
{CC120X_FS_DIVTWO, 0x03},
{CC120X_FS_DSM0, 0x33},
{CC120X_FS_DVC0, 0x17},
{CC120X_FS_PFD, 0x00},
{CC120X_FS_PRE, 0x6E},
{CC120X_FS_REG_DIV_CML, 0x1C},
{CC120X_FS_SPARE, 0xAC},
{CC120X_FS_VCO0, 0xB5},
//{CC120X_FS_CFG, 0x0B}, //136-160Mhz
{CC120X_XOSC5, 0x0E},
{CC120X_XOSC1, 0x03},
};

TER:

Cleaned up the config and now the receiver starts every time.  

Setup is as follows:

ResetCC1200(); //reset cc1200 rfsubs.c
WaitForIdleState(); //wait for idle state to be reached
registerConfig(); //12.5ms. configure radio in subs.c

WaitForIdleState(); //wait for idle state to be reached

//can now set freq since in idle mode:
FreqDes = Chan2Freq((unsigned int)Settings.RxChannel) ; // was uFixedXmtCh calc desired freq ??
SetFreq( FreqDes) ; //8=410-480, 24=136.7-160, 20=164-192 in subs.c

WaitForIdleState(); //wait for idle state to be reached

trxSpiCmdStrobe(CC120X_SRX);

config file:

//{CC120X_SYNC3, 0x55}, //was AA, 55 7:0 sets MSB sync. AA for inverted
//{CC120X_SYNC2, 0x55}, //was AA, 55, 7:0 sets MSB sync.
//{CC120X_SYNC1, 0x55}, //was AA, 55, 05 7:0 sets MSB sync.
//{CC120X_SYNC0, 0x56}, //was A9, 56 sets lsb of sync in 7:0. Orig A6
//{CC120X_SYNC_CFG0, 0x88}, //**was 88. added PQT_EN=80 & PQT_Gating_En=0x08,b00= most strict. b10=strict_sync_check=3
//{CC120X_SYNC_CFG1, 0x2C}, //**28=11 bits & 8 thresh. was 48. 4x=16bits, 8x=24bits, Ax=32 bits 7-5 len sync, 4:0=sync thresh
{CC120X_DEVIATION_M, 0x8D},
{CC120X_MODCFG_DEV_E, 0x00}, //08 for GFSK, 28 for 4GFSK GFSK/4FSK
{CC120X_DCFILT_CFG, 0x5D},
{CC120X_PREAMBLE_CFG1, 0x14}, //14=3bytes, 18=4b. 20=6b 10=2bytes e AA. was 24. 0x31=24bytes. 0x25=7bytes
//{CC120X_PREAMBLE_CFG0, 0x8A}, //**was 8A PQT_EN=08
{CC120X_IQIC, 0xCB},
{CC120X_CHAN_BW, 0xAC}, //AC=9.46khz. AA=10khz
{CC120X_MDMCFG1, 0x00}, //was E0. 80=carrier sense gate, 40=fifo en, Man mode=20, invert data=10
{CC120X_MDMCFG0, 0x45}, //transp mode
{CC120X_SYMBOL_RATE2, 0x4F}, //4f for normal 2400= 5f, 4800=6f or 9600 w/o manchester
{CC120X_SYMBOL_RATE1, 0x75},
{CC120X_SYMBOL_RATE0, 0x10},
{CC120X_AGC_REF, 0x2f}, //was 31
{CC120X_AGC_CS_THR, 0x8B}, //8B=-117, 8A=-118,88=-120, 8d=-115 was 8a, 92=-110dbm. 8F=-113, A6=-90dbm
{CC120X_AGC_CFG1, 0x51},
{CC120X_AGC_GAIN_ADJUST, 0x9c}, //9C=-100, 9D=-99. This is the RSSI offset valid when AGC_GAIN_ADJUST.GAIN_ADJUSTMENT = 0x00.
{CC120X_AGC_CFG0, 0xc7}, //8c=5 counts. Was 80=1 count for rssi
{CC120X_AGC_CFG3, 0x11}, //turns off agc freeze
{CC120X_FIFO_CFG, 0x00},
{CC120X_SETTLING_CFG, 0x01}, //do automatic autocal when going from idle to rx or tx
{CC120X_FS_CFG, 0x12},
//{CC120X_WOR_CFG0, 0x08}, //same
//{CC120X_WOR_CFG1, 0x08}, //added
//{CC120X_WOR_EVENT0_MSB, 0x01}, //0035=.6pre, 010A=1pre, 018f= 2pre, 0214=2.5pre, 029a=3pre
//{CC120X_WOR_EVENT0_LSB, 0x8f}, //
{CC120X_PKT_CFG2, 0x03}, //0c=cca mode. CRc disabled, no status byte
{CC120X_PKT_CFG1, 0x00}, // 0x01=append RSSI. Adx check & crc disabled. This line needed to rec MCDT!
{CC120X_PKT_CFG0, 0x20}, //x18 pro 6bits, x10 EMIDS 4bits. fixed length=00 in bits 6:5, bit len in bits 4:2
//{CC120X_RFEND_CFG1, 0x30}, // x30 gives return to rx after rxing
//{CC120X_RFEND_CFG0, 0x04}, //04:RX termination based on PQT. 0x1: Rx term based on CS. 0x30 gives return to rx after txing
{CC120X_PKT_LEN, 0xff}, //pktlen, packet length 02 +4 bits for emids, 6-3/4 for pro
{CC120X_IF_MIX_CFG, 0x1C},
{CC120X_FREQOFF_CFG, 0x22}, //FOC_EN=x20, FOC_KI_Factor=02 was 20
{CC120X_MDMCFG2, 0x0C},
//{CC120X_TOC_CFG, 0xC0}, //** was 40 TOC limit 2%

{CC120X_SETTLING_CFG, 0x08}, //Cal FS going from idle to rec or tx

{CC120X_FREQ2, 0x5A},
{CC120X_FREQ1, 0x00},
{CC120X_FREQ0, 0x00},

{CC120X_IF_ADC1, 0xEE}, //**needed
{CC120X_IF_ADC0, 0x10}, //**needed
{CC120X_FS_DIG1, 0x07},
{CC120X_FS_DIG0, 0xAF},
{CC120X_FS_CAL1, 0x40},
{CC120X_FS_CAL0, 0x0E},
{CC120X_FS_DIVTWO, 0x03},
{CC120X_FS_DSM0, 0x33},
{CC120X_FS_DVC0, 0x17},
{CC120X_FS_PFD, 0x00},
{CC120X_FS_PRE, 0x6E},
{CC120X_FS_REG_DIV_CML, 0x1C},
{CC120X_FS_SPARE, 0xAC},
{CC120X_FS_VCO0, 0xB5},
{CC120X_FS_CFG, 0x0B}, //band 136-160Mhz very needed
{CC120X_XOSC5, 0x0E},
{CC120X_XOSC1, 0x03},
};

Now need to make sure the transmitter works.

Thanks for your great help

John