CC1352P: Overrides for 20dBm 434MHz (Ebyte E79 module)

Hi Sivan. 

Can you share your SmartRF settings and overrides you have used so far? 

Have you accounted for the insertion loss of the IPX connector? This can be in the range of 1-3 dB. depending on the cable and the connector. 

Regards, 
Vegard

Sivan,

TI has not developed settings for 20 dBm @433 MHz since in most cases 10 dBm is the allowed power in this band. Since Ebyte has developed a module that should be able to give 20 dBm, have you checked with them which settings they have used for the internal testing of the module? You would also need a PA table. 

Thanks Vegard and TER. 

To Vegard: I post the overrides below. They are all taken from SmartRF Studio from the setting for 915MHz, 20dBm using the settings for LAUNCHXL-CC1352P-1. Settings for 868 are identical. I understand that there is loss in the connector and matching network and filter, but I hope to see a 10dBm difference between the 10dBm setting of the chip (which gives an 8dBm output, reasonable) and the 20dBm PA setting. Right now the difference is smaller. This may be due to a different low-pass filter design, but I am hoping I can squeeze another 2 or 3dB.

To TER: Yes, I asked Ebyte for the overrides that they use in their firmware but I have not received a reply yet. I understand the reason that the overrides have not been released and are not output by SmartRF Studio. No complaints :-) Regarding the power table: I think the TxStd and Tx20 overrides specify the power setting, so it works without a separate set-power command.

Here are the overrides I used to get about 15dBm output (after the matching network and IPEX connector):

uint32_t overrides_CC1352P_915_PA[] =
{
// override_tc784_tc785.xml
// Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[4:3]=0x3)
ADI_2HALFREG_OVERRIDE(0,16,0x8,0x8,17,0x1,0x1),
// Rx: Set AGC reference level to 0x2E (default: 0x2E)
HW_REG_OVERRIDE(0x609C,0x002E),
// Rx: Set RSSI offset to adjust reported RSSI by -4 dB (default: -2), trimmed for external bias and differential configuration
(uint32_t)0x000488A3,
// Set LNA IB offset factor to 0xF
(uint32_t)0x000F8883,
// Rx: Set anti-aliasing filter bandwidth to 0x0 (in ADI0, set IFAMPCTL3[7:4]=0xD)
ADI_HALFREG_OVERRIDE(0,61,0xF,0x0),
// TX: Reduce analog ramping wait time
HW_REG_OVERRIDE(0x6028,0x001A),
// override_prop_common.xml
// DC/DC regulator: In Tx with 14 dBm PA setting, use DCDCCTL5[3:0]=0xF (DITHER_EN=1 and IPEAK=7). In Rx, use default settings.
(uint32_t)0x00F788D3,
// override_prop_common_sub1g.xml
// Set RF_FSCA.ANADIV.DIV_SEL_BIAS = 1. Bits [0:16, 24, 30] are don't care..
(uint32_t)0x4001405D,
// Set RF_FSCA.ANADIV.DIV_SEL_BIAS = 1. Bits [0:16, 24, 30] are don't care..
(uint32_t)0x08141131,
(uint32_t)0xFFFFFFFF
};

// Overrides for CMD_PROP_RADIO_DIV_SETUP_PA
uint32_t overridesTxStd_CC1352P_915_PA[] =
{
// The TX Power element should always be the first in the list
TX_STD_POWER_OVERRIDE(0x013F),
// The ANADIV radio parameter based on the LO divider (0) and front-end (0) settings
(uint32_t)0x11310703,
// override_phy_tx_pa_ramp_genfsk_std.xml
// Tx: Configure PA ramping, set wait time before turning off (0x1A ticks of 16/24 us = 17.3 us).
HW_REG_OVERRIDE(0x6028,0x001A),
// Set TXRX pin to 0 in RX and high impedance in idle/TX.
HW_REG_OVERRIDE(0x60A8,0x0401),
(uint32_t)0xFFFFFFFF
};

// Overrides for CMD_PROP_RADIO_DIV_SETUP_PA
uint32_t overridesTx20_CC1352P_915_PA[] =
{
// The TX Power element should always be the first in the list
TX20_POWER_OVERRIDE(0x001B8ED2),
// The ANADIV radio parameter based on the LO divider (0) and front-end (0) settings
(uint32_t)0x11C10703,
// override_phy_tx_pa_ramp_genfsk_hpa.xml
// Tx: Configure PA ramping, set wait time before turning off (0x1F ticks of 16/24 us = 20.3 us).
HW_REG_OVERRIDE(0x6028,0x001F),
// Set TXRX pin to 0 in RX/TX and high impedance in idle.
HW_REG_OVERRIDE(0x60A8,0x0001),
(uint32_t)0xFFFFFFFF
};

Hi

Try to change the overrides in overrides_CC1352P_915_PA to the following:

uint32_t overrides_CC1352P_915_PA[] =
{
// override_tc784_tc785.xml
// Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[4:3]=0x3)
ADI_2HALFREG_OVERRIDE(0,16,0x8,0x8,17,0x1,0x1),
// Rx: Set AGC reference level to 0x20 (default: 0x2E)
HW_REG_OVERRIDE(0x609C,0x0020),
// Rx: Set RSSI offset to adjust reported RSSI by -8 dB (default: -2), trimmed for external bias and differential configuration
(uint32_t)0x000888A3,
// Set LNA IB offset factor to 0xF
(uint32_t)0x000F8883,
// Rx: Set anti-aliasing filter bandwidth to 0xD (in ADI0, set IFAMPCTL3[7:4]=0xD)
ADI_HALFREG_OVERRIDE(0,61,0xF,0xD),
// TX: Reduce analog ramping wait time
HW_REG_OVERRIDE(0x6028,0x001A),
// override_prop_common.xml
// DC/DC regulator: In Tx with 14 dBm PA setting, use DCDCCTL5[3:0]=0xF (DITHER_EN=1 and IPEAK=7). In Rx, use default settings.
(uint32_t)0x00F788D3,
// override_prop_common_sub1g.xml
// Set RF_FSCA.ANADIV.DIV_SEL_BIAS = 1. Bits [0:16, 24, 30] are don't care..
(uint32_t)0x4001405D,
// Set RF_FSCA.ANADIV.DIV_SEL_BIAS = 1. Bits [0:16, 24, 30] are don't care..
(uint32_t)0x08141131,
(uint32_t)0xFFFFFFFF
};