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CC1352P: clock loss characteristics

Part Number: CC1352P

Hi,

working with CC1352P, and the associated errata Radio_02 (low temp or poor RF matching may cause Clock Loss). I have related questions.

The errata recommends to use max +17 dBm output power unless RF matching is good and controlled, and for our use case (we don't control the customer hardware design) I'd like to get a better understanding of this.

Can you describe such a clock loss event? What is the characteristics of such?

Eg, for how long time does it persist?

Does something else on the chip become unstable or corrupt, eg RAM, registers, HF clock?

What's the risk of this happening ("if I send 1Mn packets, on how many occasions would I experience this")?

Background: using +20 dBm on sub-GHz (863 and 902 bands) on cc1352p1 Launchpads, prop radio (802.15.4) 50kbps, 2gfsk, 25k deviation, indoor temps.

We do take precautions (eg clock loss reboot and report).

  • Hi,

    Advisory radio_02 is mainly regarding operation at low temperatures ( below -20 degrees C). 

    As the errata states, if clock loss happens the device will reset.

  • Yes, it will reset if clock loss detection reset is enabled.

    And yes, agree, the errata mentions -20 degrees, but it also mentions "PCB designs not adhering to the TI recommended guidelines or in applications where antenna impedance is subject to change". And, a VSWR of 2:1 or better should be used.

    Since the 2:1 ratio is a commonly given rule of thumb of a pretty good match, I am lead to think that it's fairly easy to end up outside that pretty good match of 2:1. Eg, a product which is deployed in many different kinds of places means the RF match is always a compromise and some will have worse than 2:1.

    So what I'm looking to understand is the risk and consequences of this errata.. I'm happy to take a call or so if that format is better.

    Thanks!