Hi,
working with CC1352P, and the associated errata Radio_02 (low temp or poor RF matching may cause Clock Loss). I have related questions.
The errata recommends to use max +17 dBm output power unless RF matching is good and controlled, and for our use case (we don't control the customer hardware design) I'd like to get a better understanding of this.
Can you describe such a clock loss event? What is the characteristics of such?
Eg, for how long time does it persist?
Does something else on the chip become unstable or corrupt, eg RAM, registers, HF clock?
What's the risk of this happening ("if I send 1Mn packets, on how many occasions would I experience this")?
Background: using +20 dBm on sub-GHz (863 and 902 bands) on cc1352p1 Launchpads, prop radio (802.15.4) 50kbps, 2gfsk, 25k deviation, indoor temps.
We do take precautions (eg clock loss reboot and report).