CC1312R: GPRAM usage

GregoireGentil

Part Number: CC1312R
Other Parts Discussed in Thread: SYSCONFIG

I have a CC1312R application based on SimpleLink CC13x2 SDK.

I have nothing special in the ccfg.c file regarding the GPRAM.

In the memory allocation tab of Code Composer, GPRAM appears as 0% usage of 8k.

Is by default GPRAM in "off mode" and not used at all? If I want to use GPRAM as a cache of the SYS flash, should I add the following in my main file:

VIMSConfigure(VIMS_BASE, TRUE, TRUE);
VIMSModeSet(VIMS_BASE, VIMS_MODE_ENABLED);

How can I know if GPRAM is used in cache mode?

Let's say that now I want to "merge" the GPRAM into the SRAM. Is that possible or will they ever stay separate? Can it appear merged in the memory allocation? For such objective, I tried to add:

#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM  0x0

in the ccfg.c file. In main.c I have put:

Power_setConstraint(PowerCC26XX_SB_VIMS_CACHE_RETAIN);
Power_setConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE);

What else do I need to do? Am I going to see 88kB of SRAM after or do I need to decide which global variables go into the GPRAM and how to do that? Is GPRAM access time similar to SRAM?

Here is the content of my TIRTOS.cmd file:

--stack_size=1024 /* C stack is also used for ISR stack */

HEAPSIZE = 0x1000; /* Size of heap buffer used by HeapMem */

/* Retain interrupt vector table variable */
--retain=g_pfnVectors
/* Override default entry point. */
--entry_point ResetISR
/* Allow main() to take args */
--args 0x8
/* Suppress warnings and errors: */
/* - 10063: Warning about entry point not being _c_int00 */
/* - 16011, 16012: 8-byte alignment errors. Observed when linking in object */
/* files compiled using Keil (ARM compiler) */
--diag_suppress=10063,16011,16012

/* The following command line options are set as part of the CCS project. */
/* If you are building using the command line, or for some reason want to */
/* define them here, you can uncomment and modify these lines as needed. */
/* If you are using CCS for building, it is probably better to make any such */
/* modifications in your CCS project and leave this file alone. */
/* */
/* --heap_size=0 */
/* --stack_size=256 */
/* --library=rtsv7M3_T_le_eabi.lib */

/* The starting address of the application. Normally the interrupt vectors */
/* must be located at the beginning of the application. */
#define FLASH_BASE 0x0
#define FLASH_SIZE 0x58000
#define RAM_BASE 0x20000000
#define RAM_SIZE 0x14000
#define GPRAM_BASE 0x11000000
#define GPRAM_SIZE 0x2000

/* System memory map */

MEMORY
{
/* Application stored in and executes from internal flash */
FLASH (RX) : origin = FLASH_BASE, length = FLASH_SIZE
/* Application uses internal RAM for data */
SRAM (RWX) : origin = RAM_BASE, length = RAM_SIZE
/* Application can use GPRAM region as RAM if cache is disabled in the CCFG
(DEFAULT_CCFG_SIZE_AND_DIS_FLAGS.SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM = 0) */
GPRAM (RWX): origin = GPRAM_BASE, length = GPRAM_SIZE
}

/* Section allocation in memory */

SECTIONS
{
.intvecs : > FLASH_BASE
.text : >> FLASH
.TI.ramfunc : {} load=FLASH, run=SRAM, table(BINIT)
.const : >> FLASH
.constdata : >> FLASH
.rodata : >> FLASH
.binit : > FLASH
.cinit : > FLASH
.pinit : > FLASH
.init_array : > FLASH
.emb_text : >> FLASH
.ccfg : > FLASH (HIGH)

.vtable : > SRAM
.vtable_ram : > SRAM
vtable_ram : > SRAM
.data : > SRAM
.bss : > SRAM
.sysmem : > SRAM
.stack : > SRAM (HIGH)
.nonretenvar : > SRAM
/* Heap buffer used by HeapMem */
.priheap : {
__primary_heap_start__ = .;
. += HEAPSIZE;
__primary_heap_end__ = .;
} > SRAM align 8
.gpram : > GPRAM
}

over 4 years ago

0 Siri over 4 years ago

TI__Guru* 86731 points

Please take a look at the following and see if that answers your questions:

https://software-dl.ti.com/simplelink/esd/simplelink_cc13x2_26x2_sdk/3.30.00.03/exports/docs/proprietary-rf/proprietary-rf-users-guide/proprietary-rf-guide/memory-index.html

Siri

0 GregoireGentil over 4 years ago in reply to Siri

Expert 2330 points

Thanks. It's useful but I think that I had already everything except the linker cmd file which still confuses me. The recommendations of the page doesn't strictly apply to my cmd file.

How do I put the bss into gpram with my cmd file which I pasted in the original question? In the memory allocation, I still see a separate GPRAM 8kB. I'm expecting hoping to see a unique 88kB SRAM. Am I wrong?

0 Marie H over 4 years ago in reply to GregoireGentil

TI__Guru* 82431 points

Hi Gregoire,

Per default GPRAM is used as cache. This is determined by the ccfg sector (configured by ccfg.c or SysConfig).

SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM

If you want to use the GPRAM as RAM you should follow the steps in the guide Siri linked. There are code snippets for how to make a GPRAM section in the linker file and put bss there.

https://software-dl.ti.com/simplelink/esd/simplelink_cc13x2_26x2_sdk/3.30.00.03/exports/docs/proprietary-rf/proprietary-rf-users-guide/proprietary-rf-guide/cache-as-ram.html

0 GregoireGentil over 4 years ago in reply to Marie H

Expert 2330 points

As I said, the user guide doesn't apply well to my linker file. How do I edit my linker file?

0 Marie H over 4 years ago in reply to GregoireGentil

TI__Guru* 82431 points

Hi Gregoire,

You can find a guide to linker command file here:

https://software-dl.ti.com/ccs/esd/documents/sdto_cgt_Linker-Command-File-Primer.html

0 GregoireGentil over 4 years ago in reply to Marie H

Expert 2330 points

Is there a full example somewhere of how using GPRAM as RAM for the linker? Here is a sample IT project:

https://dev.ti.com/tirex/explore/node?compilers=ccs&node=AN9MdslFzJ7nZlXHN5eiYQ__pTTHBmu__LATEST

Moving bss to GPRAM doesn't work. The compiler complains:

"../CC1312R_7XD_TIRTOS.cmd", line 118: error #10099-D: program will not fit into available memory, or the section contains a call site that requires a trampoline that can't be generated for this section. run placement with alignment fails for section ".bss" size 0x11fda. Available memory ranges:
GPRAM size: 0x2000 unused: 0x2000 max hole: 0x2000

0 Marie H over 4 years ago in reply to GregoireGentil

TI__Guru* 82431 points

Hi Gregoire,

Yes there is a full example in the user's guide Siri and I linked you. You will need to define the GPRAM memory area as shown there.

0 GregoireGentil over 4 years ago in reply to Marie H

Expert 2330 points

as I said, it's not working:

Moving bss to GPRAM doesn't work. The compiler complains:

0 Marie H over 4 years ago in reply to GregoireGentil

TI__Guru* 82431 points

Hi Gregoire,

Is your bss section bigger than GPRAM?

You can make a new section containing only select objects and put it in GRPAM:

  reorganized_into_gpram
  {
    simple_peripheral.obj(.data)
    devinfoservice.obj(.data)
    simple_gatt_profile.obj(.data)
    icall.obj(.data)
    board.obj(.bss)
    } > GPRAM

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CC1312R: GPRAM usage