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CC3220MODA: I2S handle

Part Number: CC3220MODA

Hi TI supportters,

I config I2S:

I2S_init();

//Initialize I2S opening parameters
I2S_Params_init(&i2sParams);
i2sParams.samplingFrequency = 48000;
i2sParams.memorySlotLength = I2S_MEMORY_LENGTH_16BITS;
i2sParams.moduleRole = I2S_SLAVE;
//i2sParams.moduleRole = I2S_MASTER;
i2sParams.trueI2sFormat = (bool)true;
i2sParams.invertWS = (bool)false;
i2sParams.isMSBFirst = (bool)true;
i2sParams.isDMAUnused = (bool)false;
//i2sParams.samplingEdge = I2S_SAMPLING_EDGE_FALLING;
i2sParams.samplingEdge = I2S_SAMPLING_EDGE_RISING;
i2sParams.beforeWordPadding = 0;
i2sParams.bitsPerWord = 16;
i2sParams.afterWordPadding = 0;
i2sParams.fixedBufferLength = BUFSIZE;
i2sParams.SD0Use = I2S_SD0_OUTPUT;
//i2sParams.SD0Use = I2S_SD0_DISABLED;
i2sParams.SD1Use = I2S_SD1_INPUT;
i2sParams.SD0Channels = I2S_2_CHANNELS;
i2sParams.SD1Channels = I2S_2_CHANNELS;
//i2sParams.phaseType = I2S_PHASE_TYPE_SINGLE;
i2sParams.phaseType = I2S_PHASE_TYPE_DUAL;
i2sParams.startUpDelay = 0;
i2sParams.MCLKDivider = 40;
i2sParams.writeCallback = writeCallbackFxn ;
i2sParams.readCallback = readCallbackFxn ;
i2sParams.errorCallback = errCallbackFxn;
i2sParams.custom = NULL;
i2sHandle = I2S_open(I2S_CODEC, &i2sParams);

// Initialize the read-transactions
I2S_Transaction_init(&i2sRead1);
I2S_Transaction_init(&i2sRead2);
I2S_Transaction_init(&i2sRead3);
I2S_Transaction_init(&i2sRead4);
i2sRead1.bufPtr = i2s_read_buf[0];
i2sRead2.bufPtr = i2s_read_buf[1];
i2sRead3.bufPtr = i2s_read_buf[2];
i2sRead4.bufPtr = i2s_read_buf[3];
i2sRead1.bufSize = sizeof(i2s_read_buf[0]);
i2sRead2.bufSize = sizeof(i2s_read_buf[1]);
i2sRead3.bufSize = sizeof(i2s_read_buf[2]);
i2sRead4.bufSize = sizeof(i2s_read_buf[3]);
List_clearList(&i2sReadList);
List_put(&i2sReadList, (List_Elem*)&i2sRead1);
List_put(&i2sReadList, (List_Elem*)&i2sRead2);
List_put(&i2sReadList, (List_Elem*)&i2sRead3);
List_put(&i2sReadList, (List_Elem*)&i2sRead4);

I2S_setReadQueueHead(i2sHandle, &i2sRead1);

// Initialize the write-transactions
I2S_Transaction_init(&i2sWrite1);
I2S_Transaction_init(&i2sWrite2);
I2S_Transaction_init(&i2sWrite3);
I2S_Transaction_init(&i2sWrite4);
i2sWrite1.bufPtr = i2s_write_buf[0];
i2sWrite2.bufPtr = i2s_write_buf[1];
i2sWrite3.bufPtr = i2s_write_buf[2];
i2sWrite4.bufPtr = i2s_write_buf[3];
i2sWrite1.bufSize = sizeof(i2s_write_buf[0]);
i2sWrite2.bufSize = sizeof(i2s_write_buf[1]);
i2sWrite3.bufSize = sizeof(i2s_write_buf[2]);
i2sWrite4.bufSize = sizeof(i2s_write_buf[3]);
List_clearList(&i2sWriteList);
List_put(&i2sWriteList, (List_Elem*)&i2sWrite1);
List_put(&i2sWriteList, (List_Elem*)&i2sWrite2);
List_put(&i2sWriteList, (List_Elem*)&i2sWrite3);
List_put(&i2sWriteList, (List_Elem*)&i2sWrite4);

I2S_setWriteQueueHead(i2sHandle, &i2sWrite1);

I2S_startClocks(i2sHandle);
I2S_startWrite(i2sHandle);
I2S_startRead(i2sHandle);

And readcallback:

// Read callback
void readCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr)
{
	unsigned short* pos;
	unsigned short* pos2;
	unsigned short* pos3;
	unsigned short i;
	unsigned short dmy;
	unsigned short j;
	unsigned short k;
	unsigned short flg;
	signed short val;
	
	
    // We must remove the previous transaction (the current one is not over)
    I2S_Transaction *transactionFinished = (I2S_Transaction*)List_prev(&transactionPtr->queueElement);
	
    if(transactionFinished != NULL){
		i2s_r_finish_flg = 1;
		pos = transactionFinished->bufPtr;		
		if(1){
			j = 0;
			k = 0;
			flg = 0;
			pos2 = &i2s_af_buff[i2s_af_pos][0];		// Contain channel 1
			pos3 = &i2s_af_buff2[i2s_af_pos][0];	// Contain channel 2
			for(i=0;i<BUFSIZE;i++){		// Separate 2 channel
				if((i % 2) == 0){	
					*(pos2 + j++) = *(pos + i);
				}
				else{
					*(pos3 + k++) = *(pos + i);
				}
			}
			i2s_af_pos = (i2s_af_pos + 1) % 10;
			udp_i2s_tx_count++;
		}

		List_remove(&i2sReadList, (List_Elem*)transactionFinished);
		if(i2s_stop_trans_flg == 0){
			List_put(&i2sReadList, (List_Elem*)transactionFinished);
		}
		else{
			i2s_stop_r_flg = 1;
		}
    }
}

i2s_af_buff  contain left channel data

i2s_af_buff2 contain right channel data

I receive data through I2S interface but data at left channel somtimes change from i2s_af_buff to i2s_af_buff2 when I restart I2S.

How can I fixed left channel data at i2s_af_buff and right channel data at i2s_af_buff2 ?

Thank a lot,

Vu.

  • Hi Vu,

    Can you please clarify by what you mean when you "restart I2S"?

    Are you doing a full MCU reset, are you closing and re-opening the I2S interface, start/stopping the program in the debugger, or are you doing something else?

    Showing me your code snippet that performs this restart would be helpful.

    Regards,

    Michael

  • Hi Michael,

    I'm closing and re-opening I2S interface:

    	if(i2s_codec_seq == 0){
    		if(i2s_trans_seq == 1){	// Start I2S
    			init_i2s_ssm2604();
    			i2s_codec_seq++;
    			UART_PRINT("I2S Start\n\r");
    		}		
    	}
    	else{
    		if(i2s_trans_seq == 2){	// Stop I2S
    			I2S_stopWrite(i2sHandle);
    			I2S_stopRead(i2sHandle);
    			I2S_stopClocks(i2sHandle);
    			// Clear data in writebuff and readbuff
    			for(i=0;i<4;i++){
    				pos = &i2s_write_buf[i][0];
    				pos2 = &i2s_read_buf[i][0];
    				for(j=0;j<BUFSIZE;j++){
    					*(pos + j) = 0;
    					*(pos2 + j) = 0;
    				}
    			}
    			I2S_close(i2sHandle);
    			i2s_codec_seq = 0;
    			i2s_trans_seq = 0;
    			UART_PRINT("I2S Stopped\n\r");
    		}
    	}

    Thank you,

    Vu

  • Hi Vu,

    Thanks for providing the code you're using to start/stop the I2S interface.

    One more clarification, in your first post you show a screenshot of Audacity, where it seems like the left channel has twice as much data as expected while the right channel has no data. Is this what you see from the I2S buffers?

    I think overall, the I2S interface is not expected to be repeatedly stopped/restarted. If you perform a soft MCU reset using the code in this linked post, are you able to get the expected I2S functionality back?

    http://e2e.ti.com/support/wireless-connectivity/wifi/f/968/p/941237/3477281#3477281

    Regards,

    Michael