• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 40 subscribers
  • Views 226 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CC3351: Hardware design recommendation?

AnBer
Mastermind 30295 points
Part Number: CC3351


Tool/software:

Team,
Could you help with the below question and check if more info is available?
I saw that some are partly answered in 'CC33xx Hardware Integration https://www.ti.com/lit/pdf/swru612 '.
It could be also useful to document how the pins should be treated in case it is unused.

We are designing the schematic of a CC3351 board. We need support from your side:

  1. Power-up sequence: Could VDD_MAIN_IN(1V8) and PA_LDO_IN(3V3) be powered on at the same time? Is there a sequence here?
    -> see https://www.ti.com/lit/pdf/swru612 section 2.2.2
    Is a power-down sequence needed too?

  2. Can Wi-Fi and BLE share the SDIO interface? We don't have enough UART for CC3351 BLE.

  3. Is the Slow_clock_in necessary ? How does it affect the low power mode?

  4. How to connect ANT_SEL PIN?
    -> see section https://www.ti.com/lit/pdf/swru612 section 2.4

  5. How to connect LOGGER?
    ->https://www.ti.com/lit/pdf/swru612 section 2.2.2.1
    You can also check both M2-CC3351 (LOGGER is unused pin) and BP-CC3351 (LOGGER is connected to a 3.3V translator) schematics: https://www.ti.com/product/CC3351#hardware-development
  6. How to connect FAST_CLK_REG

Thanks in advance,

Anthony

  • 0
    TI__Intellectual 1790 points

    Hi Anthony,

    1) They should be powered on the same time and there is no sequence here.
    For a power down sequence, first bring down the nRESET line, and then shut down the power after at least 10 [µsec].

    2) Yes, Wi-Fi and BLE can share the same SDIO interface, as stated within chapter 3.6 (SDIO).

    3) The slow clock input pin (pin #34) is used in a case where an external slow clock is used. It can be generated internally, but it will cause the device to consume more power since the internal slow clock is less accurate. Hence, I recommend using the external slow clock.

    4) The antenna select (pin #15) is used in a case where you utilize antenna diversity, by implementing an RF switch. In this case you should connect this pin to the appropriate pin of the RF switch so it will be used as the switching signal. For more information regarding this pin, please refer to section 2.4 in the integration guide.

    5) The Logger pin (pin #28) is used in order to be able to capture FW logs. I recommend connecting it to a TP so when need, you'll be able to capture those logs.
    Keep in mind the TP may interfere with RD performance, so make sure you have the TP as far away as possible from the RF traces.
    As section 2.2.2.1 suggests, this pin is a SOP pin, and should stay at logic level High during power-up, but If it's connected to a host that may affect the logic level of this line, consider adding an optional pull-down/pull-up resistor(s).

    6) I assume you're referring to the FAST_CLK_REQ pin (pin #36). This pin should be left not connected.

    Best regards,

    Omri