CC3220SF: DMA based transfers from SPI being triggered from a timer

Hi Ken,

Just so I understand your setup, you are using DMA to transfer a buffer of ADC values into memory which come in via SPI, and you collect these values at certain times via PWM but are limited to waiting 30us before taking the next sample?

I'm also trying to figure out your use of a timer; it seems like you are trying to trigger a SPI transaction to transfer data via DMA into memory but I am not sure what this means.

Additional details and clarity would be helpful.

Thank you.

Brandon Liu

Hi Ken,

Based on my understanding of your system, you are using an external ADC which communicates data to the CC3220SF over SPI, and it sounds like you are limited to having 30 microsecond intervals between SPI transactions, limiting the number of samples you can read. 

I'm currently still debugging a test I'm running where I try to maximize throughput of SPI transactions on the CC3220SF, taking inspiration from the SYSCFG settings mentioned in this other thread. I'm editing the SPI Controller example where I use a logic analyzer to probe MOSI, CLK, and CSN (EN) lines and set up the spicontroller.c file to essentially ignore the peripheral device completely. I change the bit rate to the maximum (2e7) and the data size to 32. This yields a 11us latency between transactions as seen in the screenshots below without using DMA. I am also looking into the DMA channels associated with the SPI transactions to see if I can optimize better.

I hope this helps and please feel free to let me know what you think. 

Thanks for your patience.

Here's is more information from the customer:

We are using: #define Board_PWM0                   CC3220SF_LAUNCHXL_PWM6 as our ADC start conversion signal.

The goal would be to use this same signal to trigger a SPI/DMA transfer.  When we have read through the guides(DMA/PWM/SPI) we find some details but not a complete picture.

We have read through the DMA in  swru465 (starting on page 114) and  GP Timers (starting on page 281) One of the areas we have not been able to figure out is(From an email from our FW dev person:

"I also see references to bits in the timer control register that are not defined anywhere.  Specifically a bit called TnOTE.
It's referenced on page 288 of SWRU465. " 

Just so I am clear, do you need the DMA transfer as a part of SPI or is that simply what you were trying to do in an attempt to reduce the 30 us latency between SPI transactions?

Ideally the DMA would be configured in Ping-Pong and be able to free up the processor to do some checks on a group of ADC samples. If the processor is only doing ADC transfers with interrupts at the higher speeds, the ablity to make decissions on the data would be limited. 

A finally configuration might look like this:

1. PWM triggers DMA transfers VIA SPI to memory with a ping pong buffer size of 32  transfers per buffer with ADC sample to sample of 5-10us. 
2. on each buffer being full, processor would review data and drop ADC readings when  values are not in range of interest.  
   1. We are currently doing 2 sections of ADC readings, one at 30us and one at a slower pace defined by the data from the first set of readings. 
   2. We would like to be able to see more detail in the data but not save all the data to memory. Using the DMA to off load the data transfer would free up the processor to make logic desisions on the data that is collected. 
3. This process runs for up to 2 seconds with a final adc sample count of 1000  32 bit pairs.  Normal run time is more like 200ms, but we have time when the slow data collection phase is able to run for 2 seconds. 

Sounds good. I will update you over the next few days - the latest you should expect a response from me is next Monday. Thanks for your patience.