Hi,
1. Rise time for SDIO CLK is specified in the WL1273 data sheet as 4.3ns MAX. Is this spec interpreted correctly to mean that the fastest allowed transition on CLK is 4.3nS, and slower rise times are acceptable (such as 11ns), but rise times faster than 4.3nS (such as 1nS) are not acceptable.
The other interpretation is that the number 4.3 is the MAX, and then smaller numbers are allowed such as 1 nS.
2. Are there any known trends for the SDIO CLK input logic thresholds at low temperatures?
Thanks for your help!
Best Regards,
Matt
