• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 40 subscribers
  • Views 697 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

WiLink7 TCXO Clock Frequency Bias

David Harkness
Intellectual 385 points
Other Parts Discussed in Thread: WL1281

We are using Murata module (LBEL1CESEC) with WiLink7.  All application notes have been followed for HW integration.  Power rails and TCXO have been thoroughly tested (tolerance, stability, jitter, PN, signal quality, power rail, power rail noise, etc) and meet WL1281 specs where relevant.  System is operational but has a GPS transient speed bump issue - sudden peaks of speed are reported incorrectly - they correlate closely to transients in the reported parameter "Clock Frequency Bias" related to the TCXO.

NAVD software we are using:

version.h:#define SW_VERSION_STR      "NaviLink_MCP2.6_RC1.12"

version.h:#define NAVC_VERSION_STR    "Navilink_MCP2.6_BL2.0.14"

We do not understand what the parameter "Clock Frequency Bias" really means.  It is reported in m/s but TCXO frequency is cycles/s.  Can someone explain please.  We feel our TCXO circuit is stable and clean but would like to check anything that could lead us to resolve this issue.

Is there anything we could or should measure or investigate in the hardware that could cause this phenomenon.

  • 0
    TI__Guru* 85400 points

    Hi,

    I will check internally and get back to you on this.

    Regards,
    Gigi Joseph.

  • 0 in reply to Joseph Gigi
    Intellectual 385 points

    We recently came upon another specification for GPS performance for the WiLink7 buried deep in the WL128x GPS Hardware Design Guide (SWRA388) where it states that TCXO drift must be well below 5 ppb/s.  We have seen some situations where the Clock Frequency Bias changes at a greater rate than this.  Is the bias parameter directly correlated to the TCXO input signal - ie, is the TCXO input signal the only thing that could cause this change and therefore the TCXO drift must be greater than 5 ppb/s or could there be other causes, such as PLL performance or PLL power rail.  We have never seen this in all our measurements but if the TCXO signal is the only cause then we will focus our mesaurements on this specific condition and parameter.