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sdio read failed (during ifconfig wlan0 up)

Other Parts Discussed in Thread: WL1271

Can anyone provide insught into what the problem could be here?
These messages for a WL1835MODCOM8 board connected to Xilinx Zynq host
(The wlcore driver loaded correctly on boot-up) 

ifconfig wlan0 up
[ 146.908576] wlcore: PHY firmware version: Rev 8.2.0.0.212
[ 147.193035] ------------[ cut here ]------------
[ 147.197873] WARNING: CPU: 0 PID: 810 at drivers/net/wireless/ti/wlcore/sdio.c:107 wl12xx_sdio_raw_read+0x128/0x170()
[ 147.208377] Modules linked in:
[ 147.211357] CPU: 0 PID: 810 Comm: ifconfig Tainted: G W 3.14.2-xilinx-00001-gc0292a5c-dirty #1
[ 147.220910] [<c0015658>] (unwind_backtrace) from [<c00119b4>] (show_stack+0x10/0x14)
[ 147.228703] [<c00119b4>] (show_stack) from [<c0517344>] (dump_stack+0x8c/0xd0)
[ 147.235925] [<c0517344>] (dump_stack) from [<c002295c>] (warn_slowpath_common+0x60/0x84)
[ 147.243957] [<c002295c>] (warn_slowpath_common) from [<c0022a10>] (warn_slowpath_null+0x18/0x20)
[ 147.252799] [<c0022a10>] (warn_slowpath_null) from [<c0335d5c>] (wl12xx_sdio_raw_read+0x128/0x170)
[ 147.261755] [<c0335d5c>] (wl12xx_sdio_raw_read) from [<c03250ac>] (wlcore_cmd_wait_for_event_or_timeout+0x120/0x21c)
[ 147.272269] [<c03250ac>] (wlcore_cmd_wait_for_event_or_timeout) from [<c0327b5c>] (wlcore_cmd_regdomain_config_locked+0x1d4/0x264)
[ 147.284002] [<c0327b5c>] (wlcore_cmd_regdomain_config_locked) from [<c0331450>] (wl1271_hw_init+0x58/0x170)
[ 147.293728] [<c0331450>] (wl1271_hw_init) from [<c0322d60>] (wl1271_op_add_interface+0x684/0x918)
[ 147.302598] [<c0322d60>] (wl1271_op_add_interface) from [<c04e94ac>] (ieee80211_do_open+0xaec/0xb9c)
[ 147.311714] [<c04e94ac>] (ieee80211_do_open) from [<c0409248>] (__dev_open+0xa0/0xf4)
[ 147.319531] [<c0409248>] (__dev_open) from [<c0409490>] (__dev_change_flags+0x8c/0x140)
[ 147.327514] [<c0409490>] (__dev_change_flags) from [<c040955c>] (dev_change_flags+0x18/0x48)
[ 147.335947] [<c040955c>] (dev_change_flags) from [<c046401c>] (devinet_ioctl+0x2ec/0x6b0)
[ 147.344055] [<c046401c>] (devinet_ioctl) from [<c03efd8c>] (sock_ioctl+0x234/0x288)
[ 147.351760] [<c03efd8c>] (sock_ioctl) from [<c00e3fb4>] (do_vfs_ioctl+0x55c/0x61c)
[ 147.359322] [<c00e3fb4>] (do_vfs_ioctl) from [<c00e40a8>] (SyS_ioctl+0x34/0x5c)
[ 147.366613] [<c00e40a8>] (SyS_ioctl) from [<c000e660>] (ret_fast_syscall+0x0/0x48)
[ 147.374110] ---[ end trace ade924661a90291f ]---
[ 147.378766] wl1271_sdio mmc1:0001:2: sdio read failed (-123)
[ 147.384351] wlcore: ERROR reg domain conf error
[ 157.415002] mmc1: Timeout waiting for hardware interrupt.
[ 157.458070] wlcore: ERROR firmware boot failed despite 3 retries
ifconfig: SIOCSIFFLAGS: No medium found
root@microzed:~# [ 157.577426] mmc1: card 0001 removed
[ 157.705841] sdhci-arasan e0101000.ps7-sdio: card claims to support voltages below defined range
[ 157.746527] mmc1: queuing unknown CIS tuple 0x91 (3 bytes)
[ 157.771358] mmc1: new SDIO card at address 0001
[ 158.045234] wlcore: wl18xx HW: 183x or 180x, PG 2.2 (ROM 0x11)
[ 158.074870] wlcore: loaded
[ 158.077930] wlcore: driver version: xilinx-v2014.2-trd-1-gc0292a5c-dirty
[ 158.084557] wlcore: compilation time: Wed Aug 13 09:37:58 2014


Should I be reducing the SDIO Clock frequency (presently clocked at 50MHz)?
What else should I Be looking at?

The host interface signals appear ok

The relevant Device Tree bindings are:
 

/********* Wilink-8 Section start *********/
wlcore {
compatible = "wlcore";

interrupt-parent = <&ps7_scugic_0>;
gpio = <0>; /* MIO0 = Bank0 pin0 ? */

/* use edge irqs for suspend/resume */
platform-quirks = <1>;

/* if a 12xx card is there, configure the clock to WL12XX_REFCLOCK_38_XTAL */
board-ref-clock = <4>;
};

wlan_en_reg: fixedregulator@1 {
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <3300000>; /* Actually 1.8V, but this keeps the driver happy */
regulator-max-microvolt = <3300000>;

/* WLAN_EN GPIO for PS-Pmod MIO9: Bank0, pin9 */
gpio = <&ps7_gpio_0 9 0x4>;

/* WLAN card specific delay */
startup-delay-us = <70000>;
enable-active-high;
};

ps7_sd_1: ps7-sdio@e0101000 {
clock-frequency = <5000000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clkc 22>, <&clkc 33>;
compatible = "arasan,sdhci-8.9a";
interrupt-parent = <&ps7_scugic_0>;
interrupts = <0 47 4>;
reg = <0xe0101000 0x1000>;
xlnx,has-cd = <0x0>;
xlnx,has-power = <0x0>;
xlnx,has-wp = <0x0>;
vmmc-supply = <&wlan_en_reg>;
cap-power-off-card;
};

/********* Wilink-8 section end *********/

Thanks!

Peter

  • Hi Peter,

    The DT patches for the WL8 drivers can be found in: https://gforge.ti.com/gf/download/frsrelease/1161/6994/dt_pathces.zip

    I recommend that you take a look...

    Regards,
    Gigi Joseph.

  • Joseph

    Thanks for your reply. The DT patches you refer to have been applied to our build.

    Is there something specific we should be looking for in context of this SDIO read failure?

    (Any insights or additional commentary that you can provide would be very welcome....)

    Regards
    Peter Fenn

  • Hi Peter,

    How about the Pin Mux settings?
    On our reference platform, it is as below:

    +
    + /* wl12xx/wl18xx card on mmc2 */
    + mmc2_pins: pinmux_mmc2_pins {
    + pinctrl-single,pins = <
    + 0x44 0x33 /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
    + 0x48 0x33 /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
    + 0x4C 0x33 /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
    + 0x78 0x33 /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
    + 0x88 0x33 /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
    + 0x8C 0x33 /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
    + >;
    + };

    Regards,
    Gigi Joseph.

  • any resolution for this, I have exactly the same issue