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how to slow pixel clock to 1MHz CC3200

Other Parts Discussed in Thread: CC3200

The docs say that the pixel clk should not be more than 1MHz but I have not found a way to make it less than 2MHz using the camclkcfg reg (doesn't seem to work with anything other than 0x0101 and CameraClkConfig

also what do NOBT_SYNCHRO and CAM_BT_CORRECT_EN mean?

  • Hi,

    I am checking this and will get back soon.

  • Seth,

    Firstly, which camera sensor are you working with? Does it have clock dividers within for generating the PCLK from MCLK? If not, I'm assuming PCLK will follow the MCLK. And if it follows MCLK, does you camera sensor work @ 1MHz?

    And the register you are referring to configures OFF & ON time for dividing our PLL clock to generate MCLK (and not PCLK) for the camera - PCLK shall be configured/driven by the camera sensor, outside the control of CC3200.

    And for generating 1MHz MCLK, I'd want to know how you are configuring the register you mentioned in your post? Which other value did you try before concluding that it works only w/ 0x0101? Please try to configure it as below and let me know if it works:

    HWREG(0x44025000) = 0x0404;
    CameraXClkConfig(CAMERA_BASE, 24000000, 1000000);

    -Praneet

     

  • Hi the Aptina image sensor doesn't do a divide but will work at 1MHz

    I tried the settings that you mentioned and I don't get anything out of the cc3200 pxclk

  • I'm guessing that the only solution here is to use a D-flop to divide the PxClk by 2?

    I need the slower clock in order for the data going out over WIFI to keep up with the pixel data coming in.

  • has anyone tried these settings?  or any other way to get 1MHz pixel clk?

  • Yes - I've tried and it works.

    If you are using Aptina MT9d111 and configuring it to o/p raw data, you can use bellow snippet for getting MCLK of 1PCLK - Ensure that you disable the MT9D111's PLL and configure it to follow MCLK.

    static void CamControllerInit()
    {
        ArcmPeripheralEnable(ARCM_CAMERA);
        ArcmPeripheralReset(ARCM_CAMERA);
    
    
        HWREG(0x44025000) = 0x0404;
    
        CameraReset();
        CameraModeSet(CAM_NOBT_8BIT);
    
        CameraParamsConfig(CAM_HS_POL_HI, CAM_VS_POL_HI,
                           CAM_ORDERCAM_SWAP|CAM_NOBT_SYNCHRO);
    
        CameraIntRegister(CameraIntHandler);
        CameraXClkConfig(24000000,1000000);
        CameraThresholdSet(8);
        CameraIntEnable(CAM_INT_FE);
        CameraDMAEnable();
    }

    And if you are using MT9D111 in JPEG mode, I suggest you feed i/p 24MHz to camera-sensor and then configure the sensor's PLL for getting PCLK of 1MHz. 'PLL Setup' section in MT9D111's user-guide has detailed instructions.

    Let me know if you need additional information.

    -Praneet

     

  • Closing this thread - Let me know if you need any additional information.

    -/Praneet