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Connection between ARM Cortex M4 and NWP

jiayi zhang
Intellectual 360 points
Other Parts Discussed in Thread: CC3200

Hello,

After i used CC3200 launchpad for some months, i find that i can not still understand how APP Processor connected to network processor in CC3200.

I have looked for the information from document but not found. So my question is :

1. There are two SPI interface in APP processor, one is GPSPI for user, the other is for SPI flash. Communicates the APP processor with network processor through spi-flash ?

2. According to the diagram the spi flash saves the application image and data files. But if i dont use SPI-flash(Jumper not moved), then i use IAR to debug an application and it works. There are many evens (wlan events, netapp events) that must be from NWP, how dose APP processor get the events from NWP? Between NWP and APP processor is there a ram or an interface to communicate ? That is the diagram 1 from your document. And from an other document  i saw that the coummunication between them is through AHB......

Thanks for help,

Best Regards,

Zhang JiaYi

  

  • 0
    Intellectual 360 points

    In the code driverlib i have seen that there are 3 spi : SSPI, GSPI and LSPI

    SSPI: SPI flash,   GSPI : User   LSPI : Link, maybe LSPI is for the communication.

    I think maybe LSPI is very important and user should not use it or ti wants to avoid the usage of user, so we can not get any information about it.

  • 0 in reply to jiayi zhang
    TI__Mastermind 27615 points
    Hi Zhang,

    The communication is indeed through an SPI interface that is not exposed to the user.

    -Aaron
  • 0 in reply to made4engineering
    Intellectual 985 points

    Hi,


    I too discovered the LSPI only through 'following' the code. I think it would be very helpful if TI would please provide a little more information about the architecture of the CC3200. Is there any reason such critical information is buried in code and not made explicit. Even the register value for the LSPI is ommitted from the table in the TRM (indeed the LSPI isn't mentioned). This is misleading.

    I can imagine a response: "But the user doesn't need to know about the LSPI"? Yes he does. The Cortex M4 app processer is 'mine' as application programmer and I need to know everything it is doing - in small power-sensitive, embedded applications I need to know about every interrupt, every byte sent or received on peripherals, even internal, and almost where every cycle goes. And in any case, it is rare indeed when a better understanding of the HW is not beneficial.

    So please TI consider an update of the documentation which provides a fuller picture of your chip and how it works.

    Ciarán Mac Aonghusa

  • 0 in reply to Ciaran Mac Aonghusa
    TI__Mastermind 27615 points
    Hi Ciaran,

    You do make some good points. I'll discuss this with others here to see if this is possible.

    -Aaron