Other Parts Discussed in Thread: CC3100MOD, CC31XXEMUBOOST, UNIFLASH, CC3100
I am using CC3100XXEMUBOOST to format SFlash on CC3100MOD.
Setup:
CC31XXEMUBOOST Rev 3.0
Uniflash Ver: 3.2.1.00000
CC3100MODR11MAMOB jon customer board, refer to reference design.
Connection: P1.3 (UART1_TX) <-> Pin 46
P1.4 (UART1_RX) <-> Pin 47
P1.1 (VCC) <-> VBAT
P3.2 (GND) <-> GND
P1.5 (nHIB) <-> Pin 4
P2.5 (nRESET) <-> Pin35
The format failed. Please refer to the following details. Also for programming SFlash, aren Reset and nHIB connection required?
Thanks,
Leo
Debug in Uniflash enabled:
[12:38:34] Begin Format operation.
[12:38:34] INFO: > Executing Operation: Connect
[12:38:35] DEBUG: waiting and clearing uart rx buffer
[12:38:37] INFO: setting break signal
[12:38:37] DEBUG: wait for ack
[12:38:38] DEBUG: UART timeout
[12:38:38] DEBUG: --- COM Port timeout on ACK read
[12:38:38] INFO: detecting FTDI for device reset
[12:38:38] DEBUG: got 6 devices connected
[12:38:38] DEBUG: Device 0: , SN:
[12:38:38] DEBUG: Device 1: CCS MACHX , SN: I4WZ7P6O
[12:38:38] DEBUG: Device 2: CC3100-BOOST A , SN: TICC3100BP01A
[12:38:38] DEBUG: Device 3: CC3100-BOOST B , SN: TICC3100BP01B
[12:38:38] DEBUG: Device 4: , SN:
[12:38:38] DEBUG: Device 5: CC3100-BOOST D , SN: TICC3100BP01D
[12:38:38] DEBUG: Openning FTDI device to toggle nHib
[12:38:38] DEBUG: asserting nHib
[12:38:38] DEBUG: de-asserting nHib
[12:38:38] DEBUG: wait for ack
[12:38:38] INFO: connection succeeded
[12:38:38] INFO: getting storage list
[12:38:38] DEBUG: wait for ack
[12:38:38] INFO: > Executing Operation: Init
[12:38:38] INFO: reading version info
[12:38:38] DEBUG: wait for ack
[12:38:38] INFO: DEVICE CC3100 ES1.33
[12:38:38] INFO: reading version info
[12:38:38] DEBUG: wait for ack
[12:38:38] DEBUG: Bootloader version is 2, 0, 4, 0
[12:38:38] DEBUG: raw storage write
[12:38:38] DEBUG: wait for ack
[12:38:38] DEBUG: status request
[12:38:38] DEBUG: wait for ack
[12:38:38] DEBUG: BlockSize is 4096, number of blocks is 16
[12:38:38] DEBUG: erasing 13 blocks starting from 0
[12:38:39] DEBUG: wait for ack
[12:38:39] DEBUG: status request
[12:38:39] DEBUG: wait for ack
[12:38:39] DEBUG: wait for ack
[12:38:39] DEBUG: status request
[12:38:39] DEBUG: wait for ack
[12:38:39] DEBUG: wait for ack
[12:38:39] DEBUG: status request
[12:38:39] DEBUG: wait for ack
[12:38:39] DEBUG: wait for ack
[12:38:39] DEBUG: status request
[12:38:39] DEBUG: wait for ack
[12:38:39] DEBUG: wait for ack
[12:38:39] DEBUG: status request
[12:38:39] DEBUG: wait for ack
[12:38:39] DEBUG: wait for ack
[12:38:39] DEBUG: status request
[12:38:39] DEBUG: wait for ack
[12:38:39] DEBUG: wait for ack
[12:38:39] DEBUG: status request
[12:38:39] DEBUG: wait for ack
[12:38:39] DEBUG: wait for ack
[12:38:39] DEBUG: status request
[12:38:39] DEBUG: wait for ack
[12:38:40] DEBUG: wait for ack
[12:38:40] DEBUG: status request
[12:38:40] DEBUG: wait for ack
[12:38:40] DEBUG: wait for ack
[12:38:40] DEBUG: status request
[12:38:40] DEBUG: wait for ack
[12:38:40] DEBUG: wait for ack
[12:38:40] DEBUG: status request
[12:38:40] DEBUG: wait for ack
[12:38:40] DEBUG: wait for ack
[12:38:40] DEBUG: status request
[12:38:40] DEBUG: wait for ack
[12:38:40] DEBUG: wait for ack
[12:38:40] DEBUG: status request
[12:38:40] DEBUG: wait for ack
[12:38:40] DEBUG: wait for ack
[12:38:40] DEBUG: status request
[12:38:40] DEBUG: wait for ack
[12:38:40] DEBUG: status request
[12:38:40] DEBUG: wait for ack
[12:38:40] DEBUG: 0
[12:38:40] DEBUG: wait for ack
[12:38:40] DEBUG: wait for ack
[12:38:40] INFO: > Executing Operation: Format
[12:38:40] INFO: Erase storage SFLASH
[12:38:40] DEBUG: wait for ack
[12:38:41] DEBUG: status request
[12:38:41] DEBUG: wait for ack
[12:38:41] DEBUG: Error -35 : Failed write nv memory header
[12:38:41] INFO: erase storage failed
[12:38:41] INFO: erase storage completed
[12:38:41] INFO: > Executing Operation: Disconnect
[12:38:41] DEBUG: disconnecting from device . . .
[12:38:41] DEBUG: wait for ack
[12:38:41] Operation Format returned.
The board and components were designed and selected as per reference design.
