Wifi audio app running at 48k 16bit

Jo Huri

Prodigy 60 points

Other Parts Discussed in Thread: CC3200

Hello,

I would like to know what changes in the "wifi audio app" example I have to do to run it at 48k, still 16bit.

I have a CC3200 launchpad with a Audio booster pack on it.

I tried to modify the code in the AudioCodecConfig() and AudioCaptureRenderConfigure() functions.

Then I tried to send an simple frequency wave through the module and get the data in matlab.

This method works great at 16k/16bit (the default configuration of the wifi audio app), but at 48k the wave I get is very weird and awful. (I can post a picture of it if necessary) .

Here are the changes I made so far :

- for the AudioCaptureRenderConfigure() function :

how I call it :

AudioCaptureRendererConfigure(AUDIO_CODEC_16_BIT, 48000, AUDIO_CODEC_STEREO, RecordPlay, 1);

The changes I made :

if((bitsPerSample == 16)&&(bitClk==1536000))
{
MAP_PRCMI2SClockFreqSet(1536000);
MAP_I2SConfigSetExpClk(I2S_BASE,1536000,bitClk,I2S_SLOT_SIZE_16|
I2S_PORT_DMA);
}

- for the AudioCodecConfig function :

how I call it :

AudioCodecConfig(AUDIO_CODEC_TI_3254, AUDIO_CODEC_16_BIT, 48000,
AUDIO_CODEC_STEREO, AUDIO_CODEC_SPEAKER_ALL,
AUDIO_CODEC_MIC_LINE_IN);

the changes I made :

if(bitClk == 1536000) //48k st
{
AudioCodecPageSelect(TI3254_PAGE_0);

AudioCodecRegWrite(TI3254_CLK_MUX_REG, 0x03); // PLL Clock is CODEC_CLKIN @ 768.000
AudioCodecRegWrite(TI3254_CLK_PLL_P_R_REG, 0x94); // PLL is powered up, P=1, R=4
AudioCodecRegWrite(TI3254_CLK_PLL_J_REG, 0x2A); // J=42
AudioCodecRegWrite(TI3254_CLK_PLL_D_MSB_REG, 0x00); // D = 0

AudioCodecRegWrite(TI3254_CLK_NDAC_REG, 0x87); // NDAC divider powered up, NDAC = 7
AudioCodecRegWrite(TI3254_CLK_MDAC_REG, 0x82); // MDAC divider powered up, MDAC = 2
AudioCodecRegWrite(TI3254_DAC_OSR_MSB_REG, 0x01); // DOSR = 0x0180 = 384
AudioCodecRegWrite(TI3254_DAC_OSR_LSB_REG, 0x80); // DOSR = 0x0180 = 384

AudioCodecRegWrite(TI3254_CLK_NADC_REG, 0x95); // NADC divider powered up, NADC = 21
AudioCodecRegWrite(TI3254_CLK_MADC_REG, 0x82); // MADC divider powered up, MADC = 2
AudioCodecRegWrite(TI3254_ADC_OSR_REG, 0x80); // AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A)
}

Thanks in advance.

Nicolas

over 10 years ago

0 Aashish Bhanawat over 10 years ago

TI__Genius 16085 points

Hi Jo,

Can you please try either of below configurations:

R	P	J	D	MDAC	NDAC
2	1	28	0	1	14
4	1	14	0	1	14
4	2	28	0	1	14
4	3	42	0	1	14
2	1	30	0	1	15
3	1	20	0	1	15
3	2	40	0	1	15

Regards,

Aashish

0 Jo Huri over 10 years ago in reply to Aashish Bhanawat

Prodigy 60 points

Hello Aashish,

Thank you for your answer.

None of these configurations worked better than mine.

So I tried with the original one, witch is R=4,P=1,D=0,J=42,NADC=21,MADC=2 and AOSR=128

With this configuration, the final gain (including the number of channels in stereo and the number of bit per sample i.e 16) is equal to one.

For example, at 32k : 32000 x (BitsPerSamples*NbChannels) x (R*J,D/P) x (1/NADC) x (1/MADC) x (1/AOSR) = 1.

So the frequency of the ADC is equal to the desired sample rate.

I don't know if I am clear enough.

So I tried to make a comparaison between configurations at 16k,32k and 64k.

I included a picture to show you what I got.

In green :16k

In red : 32k

In blue : 64k

The wave I recorded is at 495Hz, the three waves I recorded don't seem to be at the same frequency because of their sample rates, but they are.

The wave I get at 48k is similar to the one at 64k.

It looks like the I2S input buffer of the cc3200 is repeating many samples along the wave.

Could someone explain me what I misunderstood?

0 Aashish Bhanawat over 10 years ago in reply to Jo Huri

TI__Genius 16085 points

Hi Jo,

We have tried below configuration with example code and we are getting clean audio for 48KHz sampling. Can you please try once?

if(bitClk == 1536000)
{
AudioCodecPageSelect(TI3254_PAGE_0);

AudioCodecRegWrite(TI3254_CLK_MUX_REG, 0x03); // PLL Clock is CODEC_CLKIN
AudioCodecRegWrite(TI3254_CLK_PLL_P_R_REG, 0x91); // PLL is powered up, P=1, R=1
AudioCodecRegWrite(TI3254_CLK_PLL_J_REG, 0x38); // J=56
AudioCodecRegWrite(TI3254_CLK_PLL_D_MSB_REG, 0x00); // D = 0

AudioCodecRegWrite(TI3254_CLK_NDAC_REG, 0x82); // NDAC divider powered up, NDAC = 2
AudioCodecRegWrite(TI3254_CLK_MDAC_REG, 0x87); // MDAC divider powered up, MDAC = 7
AudioCodecRegWrite(TI3254_DAC_OSR_MSB_REG, 0x00); // DOSR = 0x0080 =
AudioCodecRegWrite(TI3254_DAC_OSR_LSB_REG, 0x80); // DOSR = 0x0080 = 128

AudioCodecRegWrite(TI3254_CLK_NADC_REG, 0x82); // NADC divider powered up, NADC = 2
AudioCodecRegWrite(TI3254_CLK_MADC_REG, 0x87); // MADC divider powered up, MADC = 7
AudioCodecRegWrite(TI3254_ADC_OSR_REG, 0x80); // AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A)
}

Regards,

Aashish

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Wifi audio app running at 48k 16bit