How to make Latency of RF Backend more deterministic

Sascha Walther

Other Parts Discussed in Thread: CC3200, CC3100

Hello,

first post at e2e, please be gentle :)

I am currently working on a timing based application. I am getting great results with the CC3200 using UDP broadcasts with around 3 - 10us jitter depending on mode and compensation method i am using. this makes for a great time synchronisation protocol and i am puzzled by the brilliant performance.

BUT. The CC3200 is designed to be low power, the api is following the KISS design. Is there any way i could dig deeper into it? more options then PM_LOW_LATENCY/POWER or ALWAYS_ON. My project has little power constrains but i would be glad to understand how the rf backend pipeline works.

Thank you,

Sascha

over 10 years ago

0 Joseph Gigi over 10 years ago

TI__Guru* 85400 points

Hi,

You can take a look at: processors.wiki.ti.com/.../CC3200_Power_Management_Optimizations_and_Measurements

Regards,
Gigi Joseph.

0 Sascha Walther over 10 years ago in reply to Joseph Gigi

Prodigy 80 points

Hello,

unfortunatly no improvements in interrupt jitter have been gained. When i look at the graph i can see that there is bining, rather then a smooth gauss distribution.

More information on how the receive interrupt works would be extremly valueable.

See the attached graph for the binning example.

0 Prajay Madhavan over 10 years ago in reply to Sascha Walther

TI__Genius 11120 points

Sacha,
Unfortunately the receive interrupt algorithm is internal to TI and cannot be disclosed.

0 Sascha Walther over 10 years ago in reply to Prajay Madhavan

Prodigy 80 points

Thank you Prajay,

I do understand that TI must protect its IP, biut maybe you can help me by answering the following questions.

1. Is this delay in any way related to the application processors firmware/ServicePack? Could i switch from the CC3200 to the CC3100 and add my own processor?

2. Current tests indicate that there is no correlation between the IRQ jitter and the 40MHz clock, is there a correlation between interrupt jitter and the 32kHz clock? I would test it myself, but i already killed 2 out of 6 boards by powering down the USB port with a launchpad connected to it and the 50Ohm ground of the signal generator on XIN.

Any help would be greatly appreciated.

Sascha

0 Prajay Madhavan over 10 years ago in reply to Sascha Walther

TI__Genius 11120 points

Sascha
There is a lot of process going on between the packet detection and any interrupt generation. The packet detection happens in the PHY, then the MAC and eventually handed to the network processor. The NWP would then pass this to the application processor. All these are firmware driven and you would expect to have some jitter in the process. This would not be directly correlated to any of the system clocks as this if firmware driven.

0 Sascha Walther over 10 years ago in reply to Prajay Madhavan

Prodigy 80 points

Thank you very much.

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How to make Latency of RF Backend more deterministic