WL1837MOD: SDIO clock edge configuration

The following footnote can be found in the WL1837MOD data manual after Table 5-1 "SDIO Default Timing Characteristics":

(1) To change the data out clock edge from the falling edge (default) to the rising edge, set the configuration bit.

My questions:

1. Where/how is this configured?  What configuration bit?
2. Does this impact only the WL18xx output (i.e. SDIO reads from the host processor perspective)?  
3. Is there a corresponding change to impact the WL18xx input (i.e. SDIO writes from the host processor perspective)? 

Thanks,
Brad