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cc3100: Porting to STM32F0 (STM32F072-Nucleo-Board), Hard Fault Error

Part Number: CC3100
Other Parts Discussed in Thread: CC3100SDK

Hi,

I have a problem using the STM32F4 Port on my STM32F0 uC. I don't know if this is the correct forum for my problem.

This is a part of the example project "spi-debug-tool". The code schows test for SPI Read:

  /*Sync pattern found. If needed, complete number of read bytes to multiple of 4 (protocol align) */
    SyncCnt %= SYNC_PATTERN_LEN;
 
    if(SyncCnt > 0)                                                                                                            //debugger SyncCnt = 3
    {
        *(_u32 *)&pBuf[0] = *(_u32 *)&pBuf[4];
         sl_IfRead(FD, &pBuf[SYNC_PATTERN_LEN - SyncCnt], SyncCnt);              //<<---Hard Fault Error
    }
    else
    {
        sl_IfRead(FD, &pBuf[0], 4);
    }

If i change the SPI-Read sequence to the following code:

char testbuf[8];

int index = SYNC_PATTERN_LEN - SyncCnt;                //debugger : index = 1      and SyncCnt =3
 sl_IfRead(FD, testbuf, SyncCnt);
 for (int i = 0; i < SyncCnt; i++)
            pBuf[i + index] = testbuf[i];

....... the Hard Fault Error disappears and the spi-debug test ends successfully!

What could be the reason for this strange behaviour. I fear that I will get these problems using the more complex examples like mqtt.

Any help is very appreciated

Otto Parzhuber

Munich Univ. of Applied Sciences

  • Hi Otto,

    It looks that hard fault is related to your platform and low-level SPI driver. I don't think that someone on TI forum will be able help you with STM part.

    Few hints:
    - how is set your testbuf[] local buffer, it looks that line *(_u32 *)&pBuf[0] = *(_u32 *)&pBuf[4]; is not applied in your case
    - is not there limitation which comes from that STM32F0 is Cortex-M0 core?
    - you need find exact place inside sl_IfRead() which cause hard fault

    Jan
  • Hi Jan,
    thank you for your fast response and assistance,
    my low level SPI driver comes from Cube-HAL and I'm afraid that you are right and there are limitations from that Cortex-M0 Core.

    Greetings
    Otto
  • Have you had a look at the SPI-implementation in CC3100SDK_1.2.0\cc3100-sdk\platform\stm32discovery as this will give you a good indication of hwo it should be written...

    Mike