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CC3200MOD: Periodic noise spike - Suspected sync issue.

Part Number: CC3200MOD
Other Parts Discussed in Thread: CC3200,

This video shows the THD+N and FFT plots I am concerned by and the Oscilloscope connected across the digital path:

 

I am implementing an audio solution using the CC3200.

Currently I am using the WiFi Audio Demo but in the future I would like to stream audio from a PC using WiFi Direct.

I have modified the audio demo to remove the codec so I can evaluate the digital path using an ApX.

While most of the time the noise is low enough to be bit accurate, periodically the noise spikes to as high as -30dB.

When examining the I2S input on board 1 and I2S output on board 2 on an Oscilloscope I note that they are not exactly in sync.

How could I combat this?

  • Hi Ben,

    Thanks for the question. Please allow some time for us to get back to you.
  • Hi,

    Seems like signal integrity issues, this will require some troubleshooting on your end.
    you can try making the line between the 2 boards as short as possible, maybe add series resistor, isolating the line, If the spike seems to noise picked up from surrounding equipment, you can try running the demo in a "cleaner" environment etc.

    Regards,
    Charles O
  •  The link between the two boards is over WiFi using the UDP exactly as in the example in the SDK (processors.wiki.ti.com/.../CC3200_Wi-Fi_Audio_Application). The problem is not with harmonics or noise spikes in frequency but with noise spikes in time.

    Every few minutes what is shown in the video I linked occurs; the THD+N momentarily jumps from ~ -100 dB to ~ -30dB.

    My hypothesis is that this is caused by periodically dropped UDP packets and a result of Under or Over flow conditions in the buffer - as can be seen on the Oscilloscope at the end of the video the bit clocks of the two boards are not in perfect sync, I need some advice on what I can do about it.

  • Hi,

    just to clarify, my understanding is that you have an audio transmitter with a master and ADC and an audio receiver with another master and DAC. Are you probing the I2S connection btw one Master and converter or comparing the I2S data on the transmitter with the receiver?

    Regard?
    Charles O
  • Hi,

    Yes, my system looks like this:

    I2S Source -> (Probe) -> CC3200MOD LP 1 ---- (WiFi, UDP) ----> CC3200MOD LP 2 -> (Probe) -> I2S Sink (DAC)

    I have a device that compares the two probed signals and calculates the THD+N etc as shown in the video.

    I am using a 1 kHz Sine wave in my testing.

    Due to this being a digital uncompressed transmission I'd expect the performance to be lossless (which is what I observe except for this periodic noise spike every few minutes). Occaisionally on a UDP link packets will drop but this is a regular and predictable occurrence independent of the environment.

    Thanks and Regards,

    Ben

  • Hi,

    Since you have a known input you should be able to confirm the dropped packets by comparing the data to the output.

    Since you have 2 I2S systems, why do you expect the data capture to be in exact sync? there will be a time lag btw data transmitted and received, the clocks will also not be in sync since they are 2 different systems. Right?

    Regards,

    Charles O

  • Hi,

    Imagine one Launchpad running at 47.998 kHz and another at 48.002 kHz.

    This means that 47998 times a second the first launchpad will request an I2S data packet from my I2S source and send it over the UDP link.

    Meanwhile at the other end the second launchpad retrieves an I2S data packet and sends it to my probe 48002 times a second.

    Since the second launchpad is depleting it's buffer at 4 packets per second faster than the first launchpad is refilling it, eventually it will empty and there will be a big noise spike as extra empty I2S packets are sent to my probe.

    Or vice versa; the data being passed the other way will overflow the buffer causing missing packets (since it is being filled at 4 packets per second faster than it is being emptied).

    Perhaps, if there was a way to adjust the I2S clock using a low jitter PLL and a sync pulse sent over UDP that could mitigate it?

    Regards,

    Ben