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CC3220: cc3220 i2s master clock

Part Number: CC3220

I’ve found myself a bit confused with the I2S (McASP) on the cc3220. I was hoping you might be able to offer some guidance.

 

I’m trying to interface a cc3220 to a ADS127L01 ADC in frame sync mode.

 

From the TRM it looks as if the I2S port can only act as Master. The problem I have is that the cc3220 can generate the frame and bit clocks to the adc, but I have no idea how I can source the synchronous MCLK (for sigma delta oversampling) that is needed for the ADS127L01? Usually, I expect a audio master clock out for a SOC with I2S master mode. I’m really confused that this does not show up in the TRM or pin muxing options. Is there a hidden mode or workaround for this issue?

 

Thanks,