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CCS/CC1310: CC1310 communicate with RF studio but not code composer

Ben Duvenage22
Expert 1250 points
Part Number: CC1310
Other Parts Discussed in Thread: CC3100

Tool/software: Code Composer Studio

Hi All

Almost 18 months in the making

Finally got a custom board going.  But I'm having an issue

RF Studio can run the rf side of the cc1310 with no issues and I can send and receive over the JTAG interface ( I'm using the SmartRF06 board's JTAG interface)  But I can not run the the debugger in CSS.  I have an extra custom board that can plug in on the SmartRF06 board and that works.  but my custom board via the XDS100V3 USB debug interface Does not work.....

Any suggestion?

Ben

  • 0
    TI__Mastermind 34940 points
    Hi Ben,

    Do you mean CC1310 or CC3100?

    Are you seeing any errors in CCS console when you try debugging on your custom board? If so, could you share that?


    Regards,
    Toby
  • 0 in reply to Toby
    Expert 1250 points

    The CC1310

    Will give some feedback a bit later....

    Kind regards

    Ben

  • 0 in reply to Ben Duvenage22
    Expert 1250 points
    Cortex_M3_0: Error: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 7.0.100.1)
    Cortex_M3_0: Trouble Halting Target CPU: (Error -2064 @ 0x0) Unable to read device status. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 7.0.100.1)
    Cortex_M3_0: JTAG Communication Error: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 7.0.100.1)
  • 0 in reply to Ben Duvenage22
    Expert 1250 points
    Error connecting to the target:
    (Error -230 @ 0x0)
    The measured lengths of the JTAG IR and DR scan-paths are invalid.
    This indicates that an error exists in the link-delay or scan-path.
    (Emulation package 7.0.100.1)
  • 0 in reply to Ben Duvenage22
    Expert 1250 points
    But can use Smart RF studio to send and receive data on the RF interface....
  • 0 in reply to Ben Duvenage22
    TI__Mastermind 34940 points
    Hmm...

    Can you check the .ccxml file (in the targetConfigs folder of the CCS project)? Make sure that "Connection" is specified as "Texas Instruments XDS100V3 USB Debug Probe". Try "Test Connection" and see if that is successful.


    PS: just to clarify, the Sub1GHz forum of wireless connectivity is best suited for CC1310.
  • 0 in reply to Toby
    Expert 1250 points

    Hi

    Connection is set as Texas Instruments XDS100v3 USB Debug probe

    Here is the result of the test connection

    [Start]

    Execute the command:

    %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

    [Result]


    -----[Print the board config pathname(s)]------------------------------------

    C:\Users\Ben\AppData\Local\TEXASI~1\CCS\
        ti\0\0\BrdDat\testBoard.dat

    -----[Print the reset-command software log-file]-----------------------------

    This utility has selected a 100- or 510-class product.
    This utility will load the adapter 'jioserdesusbv3.dll'.
    The library build date was 'Dec 11 2017'.
    The library build time was '12:04:14'.
    The library package version is '7.0.100.1'.
    The library component version is '35.35.0.0'.
    The controller does not use a programmable FPGA.
    The controller has a version number of '4' (0x00000004).
    The controller has an insertion length of '0' (0x00000000).
    This utility will attempt to reset the controller.
    This utility has successfully reset the controller.

    -----[Print the reset-command hardware log-file]-----------------------------

    The scan-path will be reset by toggling the JTAG TRST signal.
    The controller is the FTDI FT2232 with USB interface.
    The link from controller to target is direct (without cable).
    The software is configured for FTDI FT2232 features.
    The controller cannot monitor the value on the EMU[0] pin.
    The controller cannot monitor the value on the EMU[1] pin.
    The controller cannot control the timing on output pins.
    The controller cannot control the timing on input pins.
    The scan-path link-delay has been set to exactly '0' (0x0000).

    -----[The log-file for the JTAG TCLK output generated from the PLL]----------

      Test  Size   Coord      MHz    Flag  Result       Description
      ~~~~  ~~~~  ~~~~~~~  ~~~~~~~~  ~~~~  ~~~~~~~~~~~  ~~~~~~~~~~~~~~~~~~~
        1     64  - 01 00  500.0kHz   O    good value   measure path length
        2     64  + 01 20  3.000MHz  [O]   good value   apply explicit tclk

    There is no hardware for measuring the JTAG TCLK frequency.

    In the scan-path tests:
    The test length was 2048 bits.
    The JTAG IR length was 10 bits.
    The JTAG DR length was 2 bits.

    The IR/DR scan-path tests used 2 frequencies.
    The IR/DR scan-path tests used 500.0kHz as the initial frequency.
    The IR/DR scan-path tests used 3.000MHz as the highest frequency.
    The IR/DR scan-path tests used 3.000MHz as the final frequency.

    -----[Measure the source and frequency of the final JTAG TCLKR input]--------

    There is no hardware for measuring the JTAG TCLK frequency.

    -----[Perform the standard path-length test on the JTAG IR and DR]-----------

    This path-length test uses blocks of 64 32-bit words.

    The test for the JTAG IR instruction path-length succeeded.
    The JTAG IR instruction path-length is 10 bits.

    The test for the JTAG DR bypass path-length succeeded.
    The JTAG DR bypass path-length is 2 bits.

    -----[Perform the Integrity scan-test on the JTAG IR]------------------------

    This test will use blocks of 64 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.

    The JTAG IR Integrity scan-test has succeeded.

    -----[Perform the Integrity scan-test on the JTAG DR]------------------------

    This test will use blocks of 64 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.

    The JTAG DR Integrity scan-test has succeeded.

    [End]

    Trying to debug I get this ( going in to debug) This is the console output

    Cortex_M3_0: GEL Output: Memory Map Initialization Complete.
    Cortex_M3_0: GEL Output: Board Reset Complete.
    Cortex_M3_0: Error: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 7.0.100.1)
    Cortex_M3_0: Trouble Halting Target CPU: (Error -2064 @ 0x0) Unable to read device status. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 7.0.100.1)
    Cortex_M3_0: JTAG Communication Error: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 7.0.100.1)
    Cortex_M3_0: Error occurred during flash operation: Could not read register R0: target is not connected
    Cortex_M3_0: Flashloader unable to erase sector 7 (code 1338623648). Sector may be locked - try mass erase operation.
    Cortex_M3_0: Error occurred during flash operation: Could not write register R5: target is not connected
    Cortex_M3_0: Error occurred during flash operation: Could not write register R6: target is not connected
    Cortex_M3_0: Error occurred during flash operation: Could not write register R0: target is not connected
    Cortex_M3_0: Error occurred during flash operation: Could not write register PC: target is not connected
    Cortex_M3_0: Error occurred during flash operation: Failed to run target
    Cortex_M3_0: Error occurred during flash operation: Could not read register R0: target is not connected
    Cortex_M3_0: Flashloader unable to erase sector 8 (code 1338623648). Sector may be locked - try mass erase operation.
    Cortex_M3_0: Error occurred during flash operation: Could not write register R5: target is not connected
    Cortex_M3_0: Error occurred during flash operation: Could not write register R6: target is not connected
    Cortex_M3_0: Error occurred during flash operation: Could not write register R0: target is not connected
    Cortex_M3_0: Error occurred during flash operation: Could not write register PC: target is not connected
    Cortex_M3_0: Error occurred during flash operation: Failed to run target
    Cortex_M3_0: Error occurred during flash operation: Could not read register R0: target is not connected
    Cortex_M3_0: Flashloader unable to erase sector 9 (code 1338623648). Sector may be locked - try mass erase operation.
    Cortex_M3_0: Error occurred during flash operation: Could not write 0x20000400: target is not connected
    Cortex_M3_0: Error occurred during flash operation: Could not write register R0: target is not connected
    Cortex_M3_0: Error occurred during flash operation: Could not write register R1: target is not connected
    Cortex_M3_0: Error occurred during flash operation: Could not write register R2: target is not connected
    Cortex_M3_0: Error occurred during flash operation: Could not write register R5: target is not connected
    Cortex_M3_0: Error occurred during flash operation: Could not write register R6: target is not connected
    Cortex_M3_0: Error occurred during flash operation: Could not write register PC: target is not connected
    Cortex_M3_0: Error occurred during flash operation: Failed to run target
    Cortex_M3_0: File Loader: Verification failed: Could not read 0x00007000: target is not connected
    Cortex_M3_0: GEL: File: C:\Users\Ben\workspace_v6_1\itcTest\Debug\itcTest.out: Load failed.

  • 0 in reply to Ben Duvenage22
    Expert 1250 points
    Some more test..... for test connection ...the previous results was for verify connection
    [Start: Texas Instruments XDS100v3 USB Debug Probe]

    Execute the command:

    %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

    [Result]


    -----[Print the board config pathname(s)]------------------------------------

    C:\Users\Ben\AppData\Local\TEXASI~1\CCS\
    ti\0\0\BrdDat\testBoard.dat

    -----[Print the reset-command software log-file]-----------------------------

    This utility has selected a 100- or 510-class product.
    This utility will load the adapter 'jioserdesusbv3.dll'.
    The library build date was 'Dec 11 2017'.
    The library build time was '12:04:14'.
    The library package version is '7.0.100.1'.
    The library component version is '35.35.0.0'.
    The controller does not use a programmable FPGA.
    The controller has a version number of '4' (0x00000004).
    The controller has an insertion length of '0' (0x00000000).
    This utility will attempt to reset the controller.
    This utility has successfully reset the controller.

    -----[Print the reset-command hardware log-file]-----------------------------

    The scan-path will be reset by toggling the JTAG TRST signal.
    The controller is the FTDI FT2232 with USB interface.
    The link from controller to target is direct (without cable).
    The software is configured for FTDI FT2232 features.
    The controller cannot monitor the value on the EMU[0] pin.
    The controller cannot monitor the value on the EMU[1] pin.
    The controller cannot control the timing on output pins.
    The controller cannot control the timing on input pins.
    The scan-path link-delay has been set to exactly '0' (0x0000).

    -----[The log-file for the JTAG TCLK output generated from the PLL]----------

    Test Size Coord MHz Flag Result Description
    ~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
    1 64 - 01 00 500.0kHz O good value measure path length
    2 64 + 01 20 3.000MHz [O] good value apply explicit tclk

    There is no hardware for measuring the JTAG TCLK frequency.

    In the scan-path tests:
    The test length was 2048 bits.
    The JTAG IR length was 10 bits.
    The JTAG DR length was 2 bits.

    The IR/DR scan-path tests used 2 frequencies.
    The IR/DR scan-path tests used 500.0kHz as the initial frequency.
    The IR/DR scan-path tests used 3.000MHz as the highest frequency.
    The IR/DR scan-path tests used 3.000MHz as the final frequency.

    -----[Measure the source and frequency of the final JTAG TCLKR input]--------

    There is no hardware for measuring the JTAG TCLK frequency.

    -----[Perform the standard path-length test on the JTAG IR and DR]-----------

    This path-length test uses blocks of 64 32-bit words.

    The test for the JTAG IR instruction path-length succeeded.
    The JTAG IR instruction path-length is 10 bits.

    The test for the JTAG DR bypass path-length succeeded.
    The JTAG DR bypass path-length is 2 bits.

    -----[Perform the Integrity scan-test on the JTAG IR]------------------------

    This test will use blocks of 64 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.

    The JTAG IR Integrity scan-test has succeeded.

    -----[Perform the Integrity scan-test on the JTAG DR]------------------------

    This test will use blocks of 64 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.

    The JTAG DR Integrity scan-test has succeeded.

    [End: Texas Instruments XDS100v3 USB Debug Probe]
  • 0 in reply to Ben Duvenage22
    TI__Mastermind 34940 points
    One more thing to try: flash your device using SmartRF Flash Programmer. Flash the *.out file generated by CCS onto the chip.

    Also, which version of CCS are you using? The most up to date version is 7.4.
  • 0 in reply to Toby
    Expert 1250 points

    I can do a mass erase and it states that it is successful but when I reconnect to the  cc1310 it tells me that is blocked

  • 0 in reply to Ben Duvenage22
    Expert 1250 points
    running css 6.1.3
    flash programmer 2
  • 0 in reply to Ben Duvenage22
    Expert 1250 points

    Ok did some more

    home work.  The TDI and TDO lines are now correct. The reset line is also good.

    I can connect to RF Studio and send/receive packets over the radio.

    Using Flash Programmer.  It tells me the device is locked. I do a mass erase and it is pass but can not read the flash memory.  I could get it to read it once and I could write to it once but now I can  not read it at all.

    Question does the XTAL (24MHz) need to run all the time, because I have a suspicion that XTAL is not stable enough.....

    Kind regards

    Ben

  • 0 in reply to Ben Duvenage22
    TI__Mastermind 34940 points
    This post has similar sounding issue: e2e.ti.com/.../2423754

    You may want to repost in the sub 1 GHz forum (e2e.ti.com/.../) to have your hardware design looked at.