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WL1835MOD: SDIO Tracelength and antenna/chip placement

Shivasharan Nagalikar
Expert 8510 points
Part Number: WL1835MOD

Team,

One of my customers have following queries, could you please help on these:

- Is it recommended to place wifi chip on top side of PCB and antenna on bottom side of PCB? If we do so, there would be via on antenna trace. Is it advisable to use via on antenna trace on PCB?

-Trace length for SDIO interface must be same. As this is of 50 Mhz signals, why need length control.

-What should be the maximum allowable length difference for SDIO interface?

Best Regards,

Shiv

  • 0
    TI__Mastermind 27080 points
    Shiv,
    Our HW expert is traveling, so it may take few days for him to reply.. Are there plans to get the schematics and layout of this board reviewed by TI?

    Thanks
  • 0 in reply to Hari Nagalla
    TI__Genius 12730 points
    Hi Shiv,

    Sorry for the late reply. Please see my responses to your questions below:

    1) Is it recommended to place wifi chip on top side of PCB and antenna on bottom side of PCB? If we do so, there would be via on antenna trace. Is it advisable to use via on antenna trace on PCB?
    [RM] There is no need to place the PCB antenna on the opposite side of the board. You can have this on the same side. the key is to ensure that the feed to the antenna is at 50 ohms and that you have a pi matching network to tune the impedance of the antenna back to 50 ohms when in any enclosure. We don't usually recommend a via in the RF path, however if you must do this it is important to model the transition from the top layer to the bottom layers as this will be an impedance mismatch and you need to account for ir.

    2) Trace length for SDIO interface must be same. As this is of 50 Mhz signals, why need length control.
    [RM] 50 MHz is still considered to be a high speed and should be controlled length. The SDIO data lines are references to the CLK so you need to ensure that all are routed as a group and maintain the same length.

    3) What should be the maximum allowable length difference for SDIO interface?
    [RM] You can assume a +/`5% mismatch at most. We also recommend that the overall length be less that 12CM.

    Thanks,
    Riz