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CC3235MODSF: Vias size for QFM package

Part Number: CC3235MODSF

Hi team,

I received inquiry about " 11.4.1 PCB Land Pattern & Thermal Vias " and LAND PATTERN EXAMPLE (Page 113) in datasheet. According to this " 11.4.1 session", TI recommended vias size are 0.2mm. Is this requirement is mandatory ? Although customer is usually implementing vias for QFN,SON,SOP and QFP package, those via size are 0.3mm (because customer 's LGA library does not have 0.2mm via size) . when customer is using 0.3mm vias., would you consider any issues/concerns?

Can I have your Expert's advice/comments on this, please?

Best regards,

Miyazaki

  • Hi Takayuki,

    There are two reasons we recommended thermal via to be 0.2mm

    1. When we designed the stencil aperture for thermal pads, we always put a 0.2mm gap between openings as outgassing path so that we will get minimum solder voids. This 0.2mm gap is normally where we put thermal vias to avoid solder paste put directly on top of vias. Solder on vias can drip through the holes during reflow.
    2. It is proven that 0.2mm vias will minimize solder drip into the holes due to surface tension.

    We have tried 0.3mm thermal via and seen lot of solder dripped through the holes. We have not tried 0.25mm thermal vias. But it depends how the customer designs their stencil. As long as no solder paste is directly printed on the vias, that would be fine.

    But the customer has to watch out solder coverage if they design the stencil with 0.25mm gap between openings.

    BR,

    Seong

  • Hi Seong,

    Thanks for comments on this. I'll share your comments, I'm wait for customer's feedback for a while.

    Best regards,

    Miyazaki