Hi team,
I received inquiry about " 11.4.1 PCB Land Pattern & Thermal Vias " and LAND PATTERN EXAMPLE (Page 113) in datasheet. According to this " 11.4.1 session", TI recommended vias size are 0.2mm. Is this requirement is mandatory ? Although customer is usually implementing vias for QFN,SON,SOP and QFP package, those via size are 0.3mm (because customer 's LGA library does not have 0.2mm via size) . when customer is using 0.3mm vias., would you consider any issues/concerns?
Can I have your Expert's advice/comments on this, please?
Best regards,
Miyazaki