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Pin Connection between CC2530 and MCU on CC2530ZNP

Jeff Jeon
Prodigy 145 points

Other Parts Discussed in Thread: CC2530

Hi,

In "CC2530_ZNP_Schematic.pdf" document, 11 pins are needed to connect between MCU and CC2530.

CC2530_DC
CC2530_DD
MRDY
SRDY
CFG0
CFG1
SO
SI
CC2530_SS
CLK
CC2530_RESET

But, I'm not sure that which pins are essential or can be hard wired.

For example, CFG0, CFG1 are not used in sample code. In CC2480 datasheet, the pins are for the type of communications.

Also, it seems MRDY and CC2530_SS can be hard wired to GND.

And, if CC2530_DC and CC2530_DD pins need only for programming, I think, it doesn't need to connect also. Right? 

Could I have any information for minimum pin connection beetween MCU and CC2530 on final product design?

 

Thank you.

 

J.J

  • 0
    TI__Genius 9325 points

    Hi Jeff,

    Besides the schematic, I would recommend you to see "CC2530ZNP Interface Specification.pdf". If you have installed ZStack 2.4.0 without changing installation path, you can find it at C:\Texas Instruments\ZStack-CC2530-2.4.0-1.4.0\Documents\CC2530. I think you will find all answers to your questions in the document.

    - Cetri

  • 0
    Prodigy 170 points

    I had the same question last week and waded thru docs to make sense of some of the so called unused pins.

    DC and DD are debug pins and go to the debug connector. See ref schemtics for other pins on the debug connector.

    You also need the debug conn. to flash the 2530.

     

    MRDY is basically asserted whenever you want the ZNP to be active. So yiu can keep it asserted and SPI deselect

    teh ZNP and the ZNP will still keep processing. So this is mandatory. Connect as output from your MCU.

    If you want to save pins and don't do async processing, combine CS with MRDY

     

    SRDY is ZNP's way of saying it is ready with data. Connect it to your MCU GPIO as an input. You can poll

    SRDY or enable an interrupt.

     

    SO, SI, CLK and SS are std SPI signals.

     

    RESET is self-explanatory

     

     

    CFG0 is basically used to tell the ZNP to operate in SPI or UART mode. In case yiu are doing SPI only

    you can connect it to high or ground (I forget which ). Or just connect it to a  GPIO and SW set it.

     

    CFG1 is to control a clock. You can ignore it or just connect it to a GPIO (as output) and play with the

    high or low settings.

    If yiu want to save GPIOs, you can connect CFG0 and 1 to GND or Vcc

     

    So min pin connections is SI, SO, CLK, SS, SRDY

     

    Hope this helps. Let me know if you need more help. I have been living and breatjing this part for a month now

    so am in a  position to help !

     

    BTW TI is reviewing my schematics this week, so if I get any feedback I will post.

     

  • 0 in reply to G Madhusudan
    Prodigy 145 points

    Thanks G Madhusudan.

     

    You said,

    "
    So min pin connections is SI, SO, CLK, SS, SRDY
    "

    But, it shuld be...

    "
    So min pin connections is SI, SO, CLK, SS, SRDY, CS(with MRDY)
    "

    Is that correct?

     

  • 0 in reply to Jeff Jeon
    Prodigy 170 points

    What I meant as minimum pin count was with reference to pins connected from teh ZNP to the host controller.

     

    MRDY should be tied to CS - that is correct.

    But CFG0 and CFG0 also should be tied high or low (I keep forgetting). So in that respects

    your design should use these pins too but since they are tied high or low it should be a minimal

    track length and is not really considered as a major routing issue. Are you doing a 2 layer or 4 layer board ?

  • 0 in reply to G Madhusudan
    Prodigy 145 points

    Sorry G Madhusudan. I couldn't reply for your comments because of other important issues.

    Anyway, I undertood now. Thank you for your help.

    I haven't thought about the number of layer yet.

    But, I don't think it makes problem because I will test with CC2530ZNP Kit at the moment.

    Thank you.