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CC2530: Some issues about CC2530.

Part Number: CC2530

Hi team,

Here's the request from the customer:

CC2530 is set to capture on the rising edge first, and after entering the capture interrupt of the rising edge, it is set to capture on the falling edge, so as to measure the time of high level. However, when using it, it is found that only the process of debugging can enter the rising edge interrupt, but cannot enter the falling edge interrupt.

The code is shown as follows:

#include <ioCC2530.h>

typedef unsigned char uchar;
typedef unsigned int uint;

unsigned char irtime=0;
#define IR P1_0
#define uint32_t unsigned int
#define uint16_t unsigned short
#define uint8_t unsigned char


unsigned char receive_ok=1;
uint32_t upCount=0;
uint16_t valueDown=0;
uint16_t valueUp=0;
uint32_t width=0;
uint32_t isUpCap=1;
uint buffer[200]={0};
char bufferId=0;


//#define leng_23
//#define leng_21

#if defined leng_23
uint8_t leng=23;
uint8_t arr[23]={0x00};
#elif defined leng_21
uint8_t leng=21;
uint8_t arr[21]={0x00};
#else
uint8_t leng=17;
uint8_t arr[17]={0x00};
#endif

void IR_Init(void)
{
P1DIR&=0XFE;//P1.0 for input mode
P1SEL|=0X01;//Peripheral function

}
void InitUart(void)
{
PERCFG &= 0xF0; //The IO position of the peripheral control register USART 0: 0 is the P0 port position 1
P0SEL = 0x0c; //P0_2, P0_3 are used as serial ports (peripheral functions)
P2DIR &= ~0XC0; //P0 takes priority as UART0

U0CSR |= 0x80; //Set to UART mode
U0GCR |= 11;
U0BAUD |= 216; //Set the baud rate to 115200
UTX0IF = 0; //UART0 TX interrupt flag is initially set to 0
}
void UartSendString(uint *Data, int len)
{
uint i;

for(i=0; i<len; i++)
{
U0DBUF = *Data++;
while(UTX0IF == 0);
UTX0IF = 0;
}
}
void InitT3(void)
{
T3CTL|=0X08;//Enable overflow interrupt
T3IE=1;//
Enable total interrupt and T3 interrupt
T3CTL|=0XE0;//128 frequency division

T3CTL&=~0X03;//auto reload
T3CTL|=0X10;//boot
EA=1;
}

void T1_Init(void)
{
PERCFG|=0X40;//Timer 1 Alternate Location 2
P2SEL&=0XEF;//Timer 1 takes precedence
T1CTL=0X0D;//128free running mode
T1CCTL2=0X41;//Rising edge capture, capture mode, timer 1 channel 2 timer enable
T1IE=1;
EA=1;//Timer 1 overflow interrupt is automatically turned on, in the register of TIMIF
}

uint ary[3]={1,2,3};


int main()
{

CLKCONCMD &= ~0x40; //Set the system clock source to 32MHZ crystal oscillator

while(CLKCONSTA & 0x40); //Wait for the crystal oscillator to stabilize to 32M
CLKCONCMD &= ~0x07; //Set the system main clock frequency to 32MHZ
IR_Init();
// Time1_Init();
T1_Init();

InitUart();
//UartSendString("usart is ok",11);
UartSendString(ary,3);
while(1)

{

if(receive_ok==0)
{
UartSendString(buffer, sizeof(buffer));
for(int ix=0;ix<200;ix++)
{
buffer[ix]=0x00;
}
receive_ok=1;


}

}

}

uint8_t a=0;


#pragma vector = T1_VECTOR
__interrupt void T1_ISR()
{
T1IF = 0;
T1STAT &= ~0x04;//clear interrupt flag
// if(T1STAT&(~0XDF))//Timer 1 overflow interrupt
// {
//
//
// irtime++;
//
// }


if(T1STAT&(~0XFB))//Edge-triggered interrupt, timer 1 channel 2 interrupt
{
if(isUpCap)//Determine whether it is a rising edge trigger
{
a=T1CC2H;
uint8_t b=T1CC2L;
valueUp=(a<<8)|b;
isUpCap=0;//Falling edge flag clear
T1CCTL2|=0X02;//Falling edge capture
irtime=0;//The overflow count value is set to 0
}
else
{


uint8_t c=T1CC2H;
uint8_t d=T1CC2L;
valueDown=(c<<8)|d;
//valueDown=(T1CC2H<<8)|T1CC2L;
isUpCap=1;//The rising edge of the flag bit is cleared
T1CCTL2|=0X01;//Rising edge capture
width=valueDown-valueUp+65536*irtime;//Calculate the time
if(bufferId>=1)
{
buffer[bufferId++]=width;
if(bufferId>184)
{
bufferId=0;
receive_ok=0;
}
}
}


}


}
//#pragma vector = T3_VECTOR
//__interrupt void T3_ISR()//2.1ms
//{
// IRCON=0X00;
// irtime++;
//}

Could you help check this case? Thanks.

Best Regards,                                                            

Nick    

  • Hi Nick,

    Since the customer is using the bitwise inclusive OR assignment operator "|=" on T1CCTL2 then the end result will eventually become 0x43 for "capture on all edges" instead of their intention.  As to why the falling edge logical code is never entered, this could be due to hardware pin bounce or the edge is missed by the time it takes to process the ISR (also from running the timer clock slower or pausing operation inside the debugger).  At some point it would be expected to enter this section due to the mismanagement of T1CCTL2, in essence the logic can become confused between the capture mode and software flag.  

    Regards,
    Ryan